HMAC Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 8.530s 260.870us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.640s 39.202us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 30.823us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.460s 679.273us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 5.120s 2.705ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 5.218m 98.471ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 30.823us 1 1 100.00
hmac_csr_aliasing 5.120s 2.705ms 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 15.200s 1.038ms 1 1 100.00
V2 back_pressure hmac_back_pressure 32.530s 3.636ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 8.430s 400.003us 1 1 100.00
hmac_test_sha384_vectors 19.680s 436.281us 1 1 100.00
hmac_test_sha512_vectors 5.311m 9.974ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 301.342us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 262.418us 1 1 100.00
hmac_test_hmac512_vectors 11.490s 376.781us 1 1 100.00
V2 burst_wr hmac_burst_wr 8.870s 1.172ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 22.572m 30.282ms 1 1 100.00
V2 error hmac_error 18.390s 1.437ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.470m 36.233ms 1 1 100.00
V2 save_and_restore hmac_smoke 8.530s 260.870us 1 1 100.00
hmac_long_msg 15.200s 1.038ms 1 1 100.00
hmac_back_pressure 32.530s 3.636ms 1 1 100.00
hmac_datapath_stress 22.572m 30.282ms 1 1 100.00
hmac_burst_wr 8.870s 1.172ms 1 1 100.00
hmac_stress_all 1.071m 1.757ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 8.530s 260.870us 1 1 100.00
hmac_long_msg 15.200s 1.038ms 1 1 100.00
hmac_back_pressure 32.530s 3.636ms 1 1 100.00
hmac_datapath_stress 22.572m 30.282ms 1 1 100.00
hmac_wipe_secret 1.470m 36.233ms 1 1 100.00
hmac_test_sha256_vectors 8.430s 400.003us 1 1 100.00
hmac_test_sha384_vectors 19.680s 436.281us 1 1 100.00
hmac_test_sha512_vectors 5.311m 9.974ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 301.342us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 262.418us 1 1 100.00
hmac_test_hmac512_vectors 11.490s 376.781us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 8.530s 260.870us 1 1 100.00
hmac_long_msg 15.200s 1.038ms 1 1 100.00
hmac_back_pressure 32.530s 3.636ms 1 1 100.00
hmac_datapath_stress 22.572m 30.282ms 1 1 100.00
hmac_burst_wr 8.870s 1.172ms 1 1 100.00
hmac_error 18.390s 1.437ms 1 1 100.00
hmac_wipe_secret 1.470m 36.233ms 1 1 100.00
hmac_test_sha256_vectors 8.430s 400.003us 1 1 100.00
hmac_test_sha384_vectors 19.680s 436.281us 1 1 100.00
hmac_test_sha512_vectors 5.311m 9.974ms 1 1 100.00
hmac_test_hmac256_vectors 9.240s 301.342us 1 1 100.00
hmac_test_hmac384_vectors 8.460s 262.418us 1 1 100.00
hmac_test_hmac512_vectors 11.490s 376.781us 1 1 100.00
hmac_stress_all 1.071m 1.757ms 1 1 100.00
V2 stress_all hmac_stress_all 1.071m 1.757ms 1 1 100.00
V2 alert_test hmac_alert_test 1.420s 16.209us 1 1 100.00
V2 intr_test hmac_intr_test 1.330s 12.599us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.450s 182.791us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.450s 182.791us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.640s 39.202us 1 1 100.00
hmac_csr_rw 1.630s 30.823us 1 1 100.00
hmac_csr_aliasing 5.120s 2.705ms 1 1 100.00
hmac_same_csr_outstanding 2.540s 482.233us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.640s 39.202us 1 1 100.00
hmac_csr_rw 1.630s 30.823us 1 1 100.00
hmac_csr_aliasing 5.120s 2.705ms 1 1 100.00
hmac_same_csr_outstanding 2.540s 482.233us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.860s 136.515us 1 1 100.00
hmac_tl_intg_err 3.810s 446.926us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.810s 446.926us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 8.530s 260.870us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.880s 781.242us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 42.460s 4.522ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 5.220s 392.531us 1 1 100.00
TOTAL 28 28 100.00