I2C Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	19.930s	1.927ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	10.770s	4.064ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.440s	52.905us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.630s	82.006us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.930s	183.190us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.000s	81.886us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.840s	117.121us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.630s	82.006us	1	1	100.00
		i2c_csr_aliasing	2.000s	81.886us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	5.900s	199.900us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	9.514m	34.057ms	1	1	100.00
V2	host_maxperf	i2c_host_perf	1.369m	6.717ms	1	1	100.00
V2	host_override	i2c_host_override	1.660s	46.986us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.260m	19.389ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	36.650s	7.412ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	2.130s	302.082us	1	1	100.00
		i2c_host_fifo_fmt_empty	3.440s	157.134us	1	1	100.00
		i2c_host_fifo_reset_rx	4.000s	906.816us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.199m	3.672ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	9.040s	603.636us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.790s	225.685us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.390s	8.750ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	2.026m	66.137ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.990s	3.370ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	10.070s	2.690ms	1	1	100.00
		i2c_target_intr_smoke	5.880s	942.768us	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.230s	536.425us	1	1	100.00
		i2c_target_fifo_reset_tx	1.790s	237.889us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	8.140s	10.901ms	1	1	100.00
		i2c_target_stress_rd	10.070s	2.690ms	1	1	100.00
		i2c_target_intr_stress_wr	16.010s	3.327ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	6.260s	3.065ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	21.730s	4.010ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	5.240s	1.172ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	6.370s	10.012ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.540s	369.487us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.110s	316.301us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	1.369m	6.717ms	1	1	100.00
		i2c_host_perf_precise	14.090s	2.507ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	9.040s	603.636us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.790s	105.963us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.910s	915.461us	1	1	100.00
		i2c_target_nack_acqfull_addr	3.180s	532.824us	1	1	100.00
		i2c_target_nack_txstretch	2.170s	154.689us	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.930s	341.594us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.520s	1.699ms	1	1	100.00
V2	alert_test	i2c_alert_test	1.600s	49.111us	1	1	100.00
V2	intr_test	i2c_intr_test	1.520s	42.082us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.260s	34.223us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.260s	34.223us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.440s	52.905us	1	1	100.00
		i2c_csr_rw	1.630s	82.006us	1	1	100.00
		i2c_csr_aliasing	2.000s	81.886us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	103.644us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.440s	52.905us	1	1	100.00
		i2c_csr_rw	1.630s	82.006us	1	1	100.00
		i2c_csr_aliasing	2.000s	81.886us	1	1	100.00
		i2c_same_csr_outstanding	1.800s	103.644us	1	1	100.00
V2		TOTAL			36	38	94.74
V2S	tl_intg_err	i2c_tl_intg_err	2.100s	432.675us	1	1	100.00
		i2c_sec_cm	1.760s	164.212us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.100s	432.675us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	5.150s	605.027us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.090s	246.712us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	17.880s	2.830ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			45	50	90.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.71628410414934362434088112536235888811435393990760886998213066198060195760159
      Line 79, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 605026573 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 605026573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.19200097612035332564730677380212751866577981760965668513492891524749498759168
      Line 116, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 2830137552 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2830137552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.112104827673642954660473611950958585142904494669957943194515459632931494203758
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 246712466 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 246712466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.97080066842550414226311244850623764966141467855801102598899050050859695923902
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10012045380 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10012045380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:627) scoreboard [scoreboard] Miscompare: DUT-Controller, dir:BusOpRead has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.6359697748585770284803737053155658036078082850780399737435922478936946289993
      Line 82, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 225684907 ps: (i2c_scoreboard.sv:627) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] Miscompare: DUT-Controller, dir:BusOpRead
        --> EXP:
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        Name            Type                Size  Value
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