KEYMGR Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_smoke	2.420s	90.990us	1	1	100.00
V1	random	keymgr_random	2.450s	105.794us	1	1	100.00
V1	csr_hw_reset	keymgr_csr_hw_reset	1.630s	67.976us	1	1	100.00
V1	csr_rw	keymgr_csr_rw	1.950s	25.286us	1	1	100.00
V1	csr_bit_bash	keymgr_csr_bit_bash	11.700s	8.646ms	1	1	100.00
V1	csr_aliasing	keymgr_csr_aliasing	3.940s	858.988us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_csr_mem_rw_with_rand_reset	2.410s	130.185us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_csr_rw	1.950s	25.286us	1	1	100.00
		keymgr_csr_aliasing	3.940s	858.988us	1	1	100.00
V1		TOTAL			6	7	85.71
V2	cfgen_during_op	keymgr_cfg_regwen	3.230s	163.575us	1	1	100.00
V2	sideload	keymgr_sideload	2.930s	375.551us	1	1	100.00
		keymgr_sideload_kmac	3.110s	96.196us	1	1	100.00
		keymgr_sideload_aes	2.380s	106.103us	1	1	100.00
		keymgr_sideload_otbn	2.890s	121.913us	1	1	100.00
V2	direct_to_disabled_state	keymgr_direct_to_disabled	3.540s	99.985us	1	1	100.00
V2	lc_disable	keymgr_lc_disable	3.430s	125.203us	1	1	100.00
V2	kmac_error_response	keymgr_kmac_rsp_err	2.720s	78.221us	1	1	100.00
V2	invalid_sw_input	keymgr_sw_invalid_input	4.780s	171.253us	1	1	100.00
V2	invalid_hw_input	keymgr_hwsw_invalid_input	3.970s	283.712us	1	1	100.00
V2	sync_async_fault_cross	keymgr_sync_async_fault_cross	2.440s	87.283us	1	1	100.00
V2	stress_all	keymgr_stress_all	21.610s	5.269ms	1	1	100.00
V2	intr_test	keymgr_intr_test	1.740s	54.571us	1	1	100.00
V2	alert_test	keymgr_alert_test	1.690s	28.872us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_tl_errors	3.050s	171.942us	1	1	100.00
V2	tl_d_illegal_access	keymgr_tl_errors	3.050s	171.942us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_csr_hw_reset	1.630s	67.976us	1	1	100.00
		keymgr_csr_rw	1.950s	25.286us	1	1	100.00
		keymgr_csr_aliasing	3.940s	858.988us	1	1	100.00
		keymgr_same_csr_outstanding	2.840s	174.190us	1	1	100.00
V2	tl_d_partial_access	keymgr_csr_hw_reset	1.630s	67.976us	1	1	100.00
		keymgr_csr_rw	1.950s	25.286us	1	1	100.00
		keymgr_csr_aliasing	3.940s	858.988us	1	1	100.00
		keymgr_same_csr_outstanding	2.840s	174.190us	1	1	100.00
V2		TOTAL			16	16	100.00
V2S	sec_cm_additional_check	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	tl_intg_err	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
		keymgr_tl_intg_err	4.410s	289.213us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_shadow_reg_errors	4.890s	1.533ms	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_shadow_reg_errors	4.890s	1.533ms	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_shadow_reg_errors	4.890s	1.533ms	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_shadow_reg_errors	4.890s	1.533ms	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_shadow_reg_errors_with_csr_rw	1.690s	14.652us	0	1	0.00
V2S	prim_count_check	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	prim_fsm_check	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_bus_integrity	keymgr_tl_intg_err	4.410s	289.213us	1	1	100.00
V2S	sec_cm_config_shadow	keymgr_shadow_reg_errors	4.890s	1.533ms	1	1	100.00
V2S	sec_cm_op_config_regwen	keymgr_cfg_regwen	3.230s	163.575us	1	1	100.00
V2S	sec_cm_reseed_config_regwen	keymgr_random	2.450s	105.794us	1	1	100.00
		keymgr_csr_rw	1.950s	25.286us	1	1	100.00
V2S	sec_cm_sw_binding_config_regwen	keymgr_random	2.450s	105.794us	1	1	100.00
		keymgr_csr_rw	1.950s	25.286us	1	1	100.00
V2S	sec_cm_max_key_ver_config_regwen	keymgr_random	2.450s	105.794us	1	1	100.00
		keymgr_csr_rw	1.950s	25.286us	1	1	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	keymgr_lc_disable	3.430s	125.203us	1	1	100.00
V2S	sec_cm_constants_consistency	keymgr_hwsw_invalid_input	3.970s	283.712us	1	1	100.00
V2S	sec_cm_intersig_consistency	keymgr_hwsw_invalid_input	3.970s	283.712us	1	1	100.00
V2S	sec_cm_hw_key_sw_noaccess	keymgr_random	2.450s	105.794us	1	1	100.00
V2S	sec_cm_output_keys_ctrl_redun	keymgr_sideload_protect	2.360s	40.369us	1	1	100.00
V2S	sec_cm_ctrl_fsm_sparse	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_data_fsm_sparse	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_ctrl_fsm_local_esc	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_ctrl_fsm_consistency	keymgr_custom_cm	3.220s	326.357us	1	1	100.00
V2S	sec_cm_ctrl_fsm_global_esc	keymgr_lc_disable	3.430s	125.203us	1	1	100.00
V2S	sec_cm_ctrl_ctr_redun	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_kmac_if_fsm_sparse	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_kmac_if_ctr_redun	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_kmac_if_cmd_ctrl_consistency	keymgr_custom_cm	3.220s	326.357us	1	1	100.00
V2S	sec_cm_kmac_if_done_ctrl_consistency	keymgr_custom_cm	3.220s	326.357us	1	1	100.00
V2S	sec_cm_reseed_ctr_redun	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_side_load_sel_ctrl_consistency	keymgr_custom_cm	3.220s	326.357us	1	1	100.00
V2S	sec_cm_sideload_ctrl_fsm_sparse	keymgr_sec_cm	7.650s	588.661us	1	1	100.00
V2S	sec_cm_ctrl_key_integrity	keymgr_custom_cm	3.220s	326.357us	1	1	100.00
V2S		TOTAL			5	6	83.33
V3	stress_all_with_rand_reset	keymgr_stress_all_with_rand_reset	5.790s	877.527us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			27	30	90.00

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

  • Test keymgr_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.keymgr_shadow_reg_errors_with_csr_rw.103057038847745398655998434937225628443741804149145608389894092002805472099712
      Line 76, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[18] & 'hffffffff)))'
        UVM_ERROR @  14651753 ps: (keymgr_csr_assert_fpv.sv:478) [ASSERT FAILED] attest_sw_binding_5_rd_A
        UVM_INFO @  14651753 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test keymgr_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.keymgr_csr_mem_rw_with_rand_reset.88988336617761438634187942522152868764994872950656038231664164424977179591281
      Line 86, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[8] & 'hffffffff)))'
        UVM_ERROR @ 130184546 ps: (keymgr_csr_assert_fpv.sv:418) [ASSERT FAILED] sealing_sw_binding_3_rd_A
        UVM_INFO @ 130184546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_vseq.sv:928) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test keymgr_stress_all_with_rand_reset has 1 failures.

    • 0.keymgr_stress_all_with_rand_reset.74269938021718440689381740443241392453648316307605802324900567633962365218197
      Line 479, in log /nightly/runs/scratch/master/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 877527304 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 877527304 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---