| V1 |
smoke |
keymgr_dpe_smoke |
15.280s |
2.532ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.720s |
20.483us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.800s |
56.083us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
7.330s |
2.382ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
6.990s |
898.588us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.940s |
98.463us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.800s |
56.083us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.990s |
898.588us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.460s |
46.342us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.520s |
70.214us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.830s |
233.704us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.830s |
233.704us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.720s |
20.483us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.800s |
56.083us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.990s |
898.588us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.230s |
42.149us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.720s |
20.483us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.800s |
56.083us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
6.990s |
898.588us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.230s |
42.149us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
5.930s |
935.597us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
4.690s |
881.181us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
3.630s |
130.867us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
3.630s |
130.867us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
3.630s |
130.867us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
3.630s |
130.867us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
3.420s |
68.499us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
5.930s |
935.597us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
5.930s |
935.597us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |