KMAC/UNMASKED Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: `7592556`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	18.030s	977.452us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	2.090s	68.829us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.750s	28.650us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	7.060s	506.284us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.250s	205.617us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.590s	273.808us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.750s	28.650us	1	1	100.00
		kmac_csr_aliasing	4.250s	205.617us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.620s	10.835us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.860s	64.506us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	30.408m	121.231ms	1	1	100.00
V2	burst_write	kmac_burst_write	1.007m	1.616ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	17.987m	34.814ms	1	1	100.00
		kmac_test_vectors_sha3_256	17.271m	149.154ms	1	1	100.00
		kmac_test_vectors_sha3_384	19.000s	4.819ms	1	1	100.00
		kmac_test_vectors_sha3_512	12.260s	3.700ms	1	1	100.00
		kmac_test_vectors_shake_128	2.286m	19.907ms	1	1	100.00
		kmac_test_vectors_shake_256	1.164m	7.452ms	1	1	100.00
		kmac_test_vectors_kmac	2.790s	77.745us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.530s	115.044us	1	1	100.00
V2	sideload	kmac_sideload	1.564m	8.346ms	1	1	100.00
V2	app	kmac_app	1.626m	7.448ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	1.325m	24.747ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	5.042m	353.739ms	1	1	100.00
V2	error	kmac_error	2.008m	23.382ms	1	1	100.00
V2	key_error	kmac_key_error	8.650s	15.681ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	1.021m	10.159ms	0	1	0.00
V2	edn_timeout_error	kmac_edn_timeout_error	10.870s	754.552us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	14.330s	242.833us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	11.890s	1.729ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.100s	35.880us	1	1	100.00
V2	stress_all	kmac_stress_all	1.228m	2.368ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.740s	13.282us	1	1	100.00
V2	alert_test	kmac_alert_test	1.680s	13.745us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	2.520s	85.451us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	2.520s	85.451us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	2.090s	68.829us	1	1	100.00
		kmac_csr_rw	1.750s	28.650us	1	1	100.00
		kmac_csr_aliasing	4.250s	205.617us	1	1	100.00
		kmac_same_csr_outstanding	2.790s	195.940us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	2.090s	68.829us	1	1	100.00
		kmac_csr_rw	1.750s	28.650us	1	1	100.00
		kmac_csr_aliasing	4.250s	205.617us	1	1	100.00
		kmac_same_csr_outstanding	2.790s	195.940us	1	1	100.00
V2		TOTAL			25	26	96.15
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.350s	637.851us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.350s	637.851us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.350s	637.851us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.350s	637.851us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	1.960s	190.466us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	27.870s	11.060ms	1	1	100.00
		kmac_tl_intg_err	1.850s	62.426us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.850s	62.426us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.100s	35.880us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	18.030s	977.452us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.564m	8.346ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.350s	637.851us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.870s	11.060ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.870s	11.060ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.870s	11.060ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	18.030s	977.452us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.100s	35.880us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.870s	11.060ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	53.590s	13.001ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	18.030s	977.452us	1	1	100.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	31.800s	5.701ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			36	40	90.00

Failure Buckets

Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 2 failures:

Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

0.kmac_shadow_reg_errors_with_csr_rw.784711641790313289924205398420500011433315104619674694115708072237577431616
Line 86, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[48] & 'hffffffff)))'
  UVM_ERROR @ 190465638 ps: (kmac_csr_assert_fpv.sv:554) [ASSERT FAILED] prefix_9_rd_A
  UVM_INFO @ 190465638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_tl_intg_err has 1 failures.

0.kmac_tl_intg_err.71116874676917041744669467132628763129744831089783111496657622357207570367505
Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

      Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[40] & 'hffffffff)))'
  UVM_ERROR @  62426479 ps: (kmac_csr_assert_fpv.sv:506) [ASSERT FAILED] prefix_1_rd_A
  UVM_INFO @  62426479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=13) has 1 failures:
- Test kmac_sideload_invalid has 1 failures.
  - 0.kmac_sideload_invalid.16239828271998709618862908503027860885448087136147950893549465753620030078601
    Line 87, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest/run.log
```
  UVM_FATAL @ 10159028276 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa1229000, Comparison=CompareOpEq, exp_data=0x1, call_count=13)
  UVM_INFO @ 10159028276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 0.kmac_stress_all_with_rand_reset.55129348482266262384776068646837720515931517022348030421280194510570503061343
    Line 117, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 5700576202 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 5700576202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```