7592556| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 2.200m | 101.830ms | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 3.000s | 14.130us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 19.913us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 247.206us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 25.750us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 4.000s | 1.697us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 19.913us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 25.750us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 18.000s | 2.875ms | 0 | 1 | 0.00 |
| mbx_stress_zero_delays | 1.017m | 1.136ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 56.000s | 4.988ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 12.000s | 15.611us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 5.000s | 4.867us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 5.000s | 4.867us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 3.000s | 14.130us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 19.913us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 25.750us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.979us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 3.000s | 14.130us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 19.913us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 25.750us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 4.000s | 20.979us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 4 | 6 | 66.67 | |||
| V2S | tl_intg_err | mbx_sec_cm | 12.000s | 17.472us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 12.552us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 10 | 14 | 71.43 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAckData d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_intg_err has 1 failures.
0.mbx_tl_intg_err.104244171981653791592099850707344116168903850279928907678500248030803639922083
Line 102, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 12551846 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x296ffc7c a_data = 0xbfa72829 a_mask = 0x2 a_size = 0x1 a_param = 0x0 a_source = 0x26 a_opcode = Get a_user = 0x24f7c d_data = 0xf1da0bd0 d_size = 0x2 d_param = 0x0 d_source = 0x1b d_opcode = AccessAckData d_error = 0 d_user = 101110100 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 12551846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.89194204989088551685761125433421768728743625081440883041772074823323829924025
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 1696562 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x3b402588 a_data = 0xd677eb0d a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xe3 a_opcode = Get a_user = 0x1efc d_data = 0xc73cc442 d_size = 0x1 d_param = 0x0 d_source = 0x47 d_opcode = AccessAckData d_error = 0 d_user = 1001111110111 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 1696562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_*/rtl/mbx_ombx.sv,286): Assertion ReadyAssertedWhenRead_A has failed has 1 failures:
0.mbx_stress.79122316699532496052541100018266940575013599473027986088646269896028985937503
Line 113, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest/run.log
xmsim: *E,ASRTST (/nightly/runs/scratch/master/mbx-sim-xcelium/default/fusesoc-work/src/lowrisc_ip_mbx_0.1/rtl/mbx_ombx.sv,286): (time 2874724491 PS) Assertion tb.dut.u_ombx.ReadyAssertedWhenRead_A has failed
UVM_ERROR @ 2874724491 ps: (mbx_ombx.sv:286) [ASSERT FAILED] ReadyAssertedWhenRead_A
UVM_INFO @ 2874724491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Invalid, value: * a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_errors.52624543953497125104592883728531277599233570123797447689398322282565999073813
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 4866636 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x84141ab5 a_data = 0xdeb93b62 a_mask = 0x2 a_size = 0x0 a_param = 0x0 a_source = 0x94 a_opcode = Invalid, value: 3 a_user = 0x241cd d_data = 0xa066fe63 d_size = 0x3 d_param = 0x0 d_source = 0x25 d_opcode = AccessAck d_error = 0 d_user = 11101101000001 d_sink = 0 req_abort_after_a_valid_len = 1 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4866636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---