OTBN Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke otbn_smoke 32.000s 157.303us 1 1 100.00
V1 single_binary otbn_single 18.000s 40.779us 1 1 100.00
V1 csr_hw_reset otbn_csr_hw_reset 6.000s 60.529us 1 1 100.00
V1 csr_rw otbn_csr_rw 6.000s 16.586us 1 1 100.00
V1 csr_bit_bash otbn_csr_bit_bash 7.000s 125.843us 1 1 100.00
V1 csr_aliasing otbn_csr_aliasing 6.000s 21.005us 1 1 100.00
V1 csr_mem_rw_with_rand_reset otbn_csr_mem_rw_with_rand_reset 10.000s 74.687us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr otbn_csr_rw 6.000s 16.586us 1 1 100.00
otbn_csr_aliasing 6.000s 21.005us 1 1 100.00
V1 mem_walk otbn_mem_walk 20.000s 1.641ms 1 1 100.00
V1 mem_partial_access otbn_mem_partial_access 13.000s 209.995us 1 1 100.00
V1 TOTAL 9 9 100.00
V2 reset_recovery otbn_reset 24.000s 66.268us 1 1 100.00
V2 multi_error otbn_multi_err 55.000s 296.626us 1 1 100.00
V2 back_to_back otbn_multi 34.000s 633.369us 1 1 100.00
V2 stress_all otbn_stress_all 22.000s 236.398us 1 1 100.00
V2 lc_escalation otbn_escalate 9.000s 22.744us 1 1 100.00
V2 zero_state_err_urnd otbn_zero_state_err_urnd 6.000s 35.705us 1 1 100.00
V2 sw_errs_fatal_chk otbn_sw_errs_fatal_chk 8.000s 124.470us 1 1 100.00
V2 alert_test otbn_alert_test 6.000s 13.657us 1 1 100.00
V2 intr_test otbn_intr_test 6.000s 74.408us 1 1 100.00
V2 tl_d_oob_addr_access otbn_tl_errors 6.000s 72.164us 1 1 100.00
V2 tl_d_illegal_access otbn_tl_errors 6.000s 72.164us 1 1 100.00
V2 tl_d_outstanding_access otbn_csr_hw_reset 6.000s 60.529us 1 1 100.00
otbn_csr_rw 6.000s 16.586us 1 1 100.00
otbn_csr_aliasing 6.000s 21.005us 1 1 100.00
otbn_same_csr_outstanding 7.000s 26.689us 1 1 100.00
V2 tl_d_partial_access otbn_csr_hw_reset 6.000s 60.529us 1 1 100.00
otbn_csr_rw 6.000s 16.586us 1 1 100.00
otbn_csr_aliasing 6.000s 21.005us 1 1 100.00
otbn_same_csr_outstanding 7.000s 26.689us 1 1 100.00
V2 TOTAL 11 11 100.00
V2S mem_integrity otbn_imem_err 7.000s 78.887us 1 1 100.00
otbn_dmem_err 9.000s 55.062us 1 1 100.00
V2S internal_integrity otbn_alu_bignum_mod_err 8.000s 38.693us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 65.912us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 108.955us 1 1 100.00
otbn_urnd_err 9.000s 44.434us 1 1 100.00
V2S illegal_bus_access otbn_illegal_mem_acc 7.000s 53.260us 1 1 100.00
V2S otbn_mem_gnt_acc_err otbn_mem_gnt_acc_err 7.000s 19.343us 1 1 100.00
V2S otbn_non_sec_partial_wipe otbn_partial_wipe 7.000s 27.834us 1 1 100.00
V2S tl_intg_err otbn_sec_cm 1.667m 3.151ms 1 1 100.00
otbn_tl_intg_err 11.000s 599.945us 1 1 100.00
V2S passthru_mem_tl_intg_err otbn_passthru_mem_tl_intg_err 25.000s 1.015ms 1 1 100.00
V2S prim_fsm_check otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S prim_count_check otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_mem_scramble otbn_smoke 32.000s 157.303us 1 1 100.00
V2S sec_cm_data_mem_integrity otbn_dmem_err 9.000s 55.062us 1 1 100.00
V2S sec_cm_instruction_mem_integrity otbn_imem_err 7.000s 78.887us 1 1 100.00
V2S sec_cm_bus_integrity otbn_tl_intg_err 11.000s 599.945us 1 1 100.00
V2S sec_cm_controller_fsm_global_esc otbn_escalate 9.000s 22.744us 1 1 100.00
V2S sec_cm_controller_fsm_local_esc otbn_imem_err 7.000s 78.887us 1 1 100.00
otbn_dmem_err 9.000s 55.062us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 35.705us 1 1 100.00
otbn_illegal_mem_acc 7.000s 53.260us 1 1 100.00
otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_controller_fsm_sparse otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_scramble_key_sideload otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_local_esc otbn_imem_err 7.000s 78.887us 1 1 100.00
otbn_dmem_err 9.000s 55.062us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 35.705us 1 1 100.00
otbn_illegal_mem_acc 7.000s 53.260us 1 1 100.00
otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_scramble_ctrl_fsm_sparse otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_global_esc otbn_escalate 9.000s 22.744us 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_local_esc otbn_imem_err 7.000s 78.887us 1 1 100.00
otbn_dmem_err 9.000s 55.062us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 35.705us 1 1 100.00
otbn_illegal_mem_acc 7.000s 53.260us 1 1 100.00
otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_start_stop_ctrl_fsm_sparse otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_data_reg_sw_sca otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_ctrl_redun otbn_ctrl_redun 6.000s 15.660us 1 1 100.00
V2S sec_cm_pc_ctrl_flow_redun otbn_pc_ctrl_flow_redun 8.000s 12.834us 1 1 100.00
V2S sec_cm_rnd_bus_consistency otbn_rnd_sec_cm 31.000s 459.614us 1 1 100.00
V2S sec_cm_rnd_rng_digest otbn_rnd_sec_cm 31.000s 459.614us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_integrity otbn_rf_base_intg_err 11.000s 41.578us 1 1 100.00
V2S sec_cm_rf_base_data_reg_sw_glitch_detect otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_stack_wr_ptr_ctr_redun otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_integrity otbn_rf_bignum_intg_err 12.000s 230.693us 1 1 100.00
V2S sec_cm_rf_bignum_data_reg_sw_glitch_detect otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_loop_stack_ctr_redun otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S sec_cm_loop_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 13.206us 1 1 100.00
V2S sec_cm_call_stack_addr_integrity otbn_stack_addr_integ_chk 7.000s 13.206us 1 1 100.00
V2S sec_cm_start_stop_ctrl_state_consistency otbn_sec_wipe_err 7.000s 30.604us 1 1 100.00
V2S sec_cm_data_mem_sec_wipe otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_instruction_mem_sec_wipe otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_data_reg_sw_sec_wipe otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_write_mem_integrity otbn_multi 34.000s 633.369us 1 1 100.00
V2S sec_cm_ctrl_flow_count otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_ctrl_flow_sca otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_data_mem_sw_noaccess otbn_sw_no_acc 16.000s 310.650us 1 1 100.00
V2S sec_cm_key_sideload otbn_single 18.000s 40.779us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun otbn_sec_cm 1.667m 3.151ms 1 1 100.00
V2S TOTAL 20 20 100.00
V3 stress_all_with_rand_reset otbn_stress_all_with_rand_reset 4.317m 1.115ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 41 41 100.00