ROM_CTRL/64KB Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 7.980s 768.202us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 9.150s 816.083us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 7.510s 837.265us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 7.450s 304.004us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.840s 379.735us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 8.120s 589.547us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 7.510s 837.265us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 379.735us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.070s 353.033us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 8.340s 601.013us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.560s 743.926us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 19.710s 9.621ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 12.420s 397.698us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 10.300s 297.696us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 7.760s 700.380us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 7.760s 700.380us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 9.150s 816.083us 1 1 100.00
rom_ctrl_csr_rw 7.510s 837.265us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 379.735us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.300s 1.105ms 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 9.150s 816.083us 1 1 100.00
rom_ctrl_csr_rw 7.510s 837.265us 1 1 100.00
rom_ctrl_csr_aliasing 5.840s 379.735us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.300s 1.105ms 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 26.450s 756.066us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
rom_ctrl_tl_intg_err 36.660s 2.744ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 7.980s 768.202us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 7.980s 768.202us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 7.980s 768.202us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 36.660s 2.744ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
rom_ctrl_kmac_err_chk 12.420s 397.698us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.672m 4.163ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 26.450s 756.066us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 2.623m 1.708ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.602m 7.884ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00