RV_TIMER Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	1.550s	36.885us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	1.730s	54.847us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	1.760s	15.246us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	3.620s	1.643ms	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	1.640s	29.354us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	2.310s	37.034us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	1.760s	15.246us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	29.354us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.740s	623.917us	1	1	100.00
V2	disabled	rv_timer_disabled	4.240s	2.782ms	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	1.590s	63.381us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	1.590s	63.381us	1	1	100.00
V2	stress	rv_timer_stress_all	1.620s	309.311us	1	1	100.00
V2	alert_test	rv_timer_alert_test	1.610s	36.101us	1	1	100.00
V2	intr_test	rv_timer_intr_test	1.430s	42.896us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	1.860s	64.311us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	1.860s	64.311us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	1.730s	54.847us	1	1	100.00
		rv_timer_csr_rw	1.760s	15.246us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	29.354us	1	1	100.00
		rv_timer_same_csr_outstanding	1.640s	55.736us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	1.730s	54.847us	1	1	100.00
		rv_timer_csr_rw	1.760s	15.246us	1	1	100.00
		rv_timer_csr_aliasing	1.640s	29.354us	1	1	100.00
		rv_timer_same_csr_outstanding	1.640s	55.736us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	rv_timer_sec_cm	1.710s	60.389us	1	1	100.00
		rv_timer_tl_intg_err	2.250s	237.794us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	2.250s	237.794us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	20.170s	9.065ms	1	1	100.00
V3		TOTAL			1	1	100.00
	Unmapped tests	rv_timer_min	1.500s	43.498us	1	1	100.00
		rv_timer_max	1.740s	17.124us	1	1	100.00
		TOTAL			19	19	100.00