SPI_DEVICE/1R1W Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	2.366m	98.386ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.830s	21.886us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	3.270s	170.344us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.990s	639.229us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.390s	115.155us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.050s	311.112us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	3.270s	170.344us	1	1	100.00
		spi_device_csr_aliasing	6.390s	115.155us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.550s	20.814us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.930s	37.360us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.740s	21.094us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.720s	1.338us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.550s	4.319us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	3.160s	694.828us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	3.160s	694.828us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	9.520s	5.994ms	1	1	100.00
		spi_device_tpm_sts_read	1.660s	38.382us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.730s	22.078us	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	7.100s	857.448us	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.020s	909.110us	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.020s	909.110us	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	3.470s	1.720ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	3.470s	1.720ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	3.470s	1.720ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	3.470s	1.720ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	3.470s	1.720ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.740s	598.694us	1	1	100.00
V2	mailbox_command	spi_device_mailbox	37.070s	29.615ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	37.070s	29.615ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	37.070s	29.615ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	17.480s	7.986ms	1	1	100.00
		spi_device_read_buffer_direct	4.230s	749.071us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	37.070s	29.615ms	1	1	100.00
		spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	31.350s	42.130ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.430s	336.314us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.430s	336.314us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	2.366m	98.386ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	37.070s	3.332ms	1	1	100.00
V2	stress_all	spi_device_stress_all	3.100m	203.069ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.540s	32.802us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.670s	20.695us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	2.850s	96.457us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	2.850s	96.457us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.830s	21.886us	1	1	100.00
		spi_device_csr_rw	3.270s	170.344us	1	1	100.00
		spi_device_csr_aliasing	6.390s	115.155us	1	1	100.00
		spi_device_same_csr_outstanding	3.170s	40.840us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.830s	21.886us	1	1	100.00
		spi_device_csr_rw	3.270s	170.344us	1	1	100.00
		spi_device_csr_aliasing	6.390s	115.155us	1	1	100.00
		spi_device_same_csr_outstanding	3.170s	40.840us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.080s	346.689us	1	1	100.00
		spi_device_tl_intg_err	11.090s	2.825ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	11.090s	2.825ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	2.020m	28.515ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.92926324746251217774989104311461938891442462391185274389144211518552134737532
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1147004 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[50])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1147004 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1147004 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[946])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.9334359252019585243729226728715166075341503881679734044486827342780208770235
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1895927 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x8a7fe3 [100010100111111111100011] vs 0x0 [0])
        UVM_ERROR @   1956927 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6cf490 [11011001111010010010000] vs 0x0 [0])
        UVM_ERROR @   2025927 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa2f0c [10100010111100001100] vs 0x0 [0])
        UVM_ERROR @   2091927 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb8b6ab [101110001011011010101011] vs 0x0 [0])
        UVM_ERROR @   2160927 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4381d7 [10000111000000111010111] vs 0x0 [0])