SPI_HOST Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	54.000s	4.833ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	27.939us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	17.071us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	6.000s	952.565us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	28.616us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	31.645us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.616us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	16.913us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	49.393us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	106.714us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	5.000s	309.336us	1	1	100.00
		spi_host_error_cmd	4.000s	54.590us	1	1	100.00
		spi_host_event	10.000s	3.049ms	1	1	100.00
V2	clock_rate	spi_host_speed	4.000s	38.658us	1	1	100.00
V2	speed	spi_host_speed	4.000s	38.658us	1	1	100.00
V2	chip_select_timing	spi_host_speed	4.000s	38.658us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	101.996us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	3.000s	37.072us	1	1	100.00
V2	cpol_cpha	spi_host_speed	4.000s	38.658us	1	1	100.00
V2	full_cycle	spi_host_speed	4.000s	38.658us	1	1	100.00
V2	duplex	spi_host_smoke	54.000s	4.833ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	54.000s	4.833ms	1	1	100.00
V2	stress_all	spi_host_stress_all	33.000s	5.394ms	1	1	100.00
V2	spien	spi_host_spien	9.000s	2.497ms	1	1	100.00
V2	stall	spi_host_status_stall	2.200m	42.308ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	32.000s	1.681ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	5.000s	309.336us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	34.460us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	27.770us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	104.774us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	104.774us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	27.939us	1	1	100.00
		spi_host_csr_rw	3.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.616us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	24.303us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	27.939us	1	1	100.00
		spi_host_csr_rw	3.000s	17.071us	1	1	100.00
		spi_host_csr_aliasing	5.000s	28.616us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	24.303us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	95.752us	1	1	100.00
		spi_host_sec_cm	4.000s	87.554us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	95.752us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.050m	200.000ms	0	1	0.00
		TOTAL			25	26	96.15

Failure Buckets

• UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
  • Test spi_host_upper_range_clkdiv has 1 failures.

    • 0.spi_host_upper_range_clkdiv.60913678654879329272737917260381325887390693815243686732402327427305160520018
      Line 112, in log /nightly/runs/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest/run.log

        UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
        UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---