SRAM_CTRL/MAIN Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	12.180s	2.001ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	42.859us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.710s	50.058us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.310s	133.421us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.760s	13.673us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	3.750s	774.064us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.710s	50.058us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	13.673us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	3.661m	27.635ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	1.573m	4.387ms	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	2.452m	14.106ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.756m	3.380ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	21.513m	150.538ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.728m	29.442ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	22.090s	5.753ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.153m	10.279ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	14.310s	2.562ms	1	1	100.00
		sram_ctrl_partial_access_b2b	3.837m	13.881ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	1.017m	801.979us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	4.960s	2.665ms	1	1	100.00
		sram_ctrl_throughput_w_readback	7.510s	8.350ms	1	1	100.00
V2	regwen	sram_ctrl_regwen	10.070m	11.163ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	3.490s	1.346ms	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	22.311m	82.365ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.750s	55.544us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.310s	137.725us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.310s	137.725us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	42.859us	1	1	100.00
		sram_ctrl_csr_rw	1.710s	50.058us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	13.673us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	47.042us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	42.859us	1	1	100.00
		sram_ctrl_csr_rw	1.710s	50.058us	1	1	100.00
		sram_ctrl_csr_aliasing	1.760s	13.673us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.610s	47.042us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	41.350s	29.361ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
		sram_ctrl_tl_intg_err	2.550s	120.076us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.550s	120.076us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	10.070m	11.163ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	10.070m	11.163ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.710s	50.058us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.153m	10.279ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.153m	10.279ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.153m	10.279ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	22.090s	5.753ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	4.140s	686.543us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	41.350s	29.361ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	4.330s	703.832us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	12.180s	2.001ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	12.180s	2.001ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.153m	10.279ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	22.090s	5.753ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	12.180s	2.001ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.570s	6.120us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	17.600s	1.340ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.62713566568761022366812789731577405582588742101777265231509107733348114496774
      Line 95, in log /nightly/runs/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6120191 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6120191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---