SRAM_CTRL/RET Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	26.370s	501.901us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.640s	20.485us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.620s	59.625us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.890s	103.397us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.770s	21.171us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.780s	54.295us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.620s	59.625us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	21.171us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	6.480s	366.776us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	5.060s	156.880us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	7.931m	35.841ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	3.503m	3.625ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	17.250s	4.101ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	5.520m	3.450ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	11.560s	14.479ms	1	1	100.00
V2	executable	sram_ctrl_executable	4.616m	10.220ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	13.830s	3.774ms	1	1	100.00
		sram_ctrl_partial_access_b2b	5.557m	71.685ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.020s	137.300us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	11.000s	211.839us	1	1	100.00
		sram_ctrl_throughput_w_readback	52.270s	562.036us	1	1	100.00
V2	regwen	sram_ctrl_regwen	35.590s	2.215ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.570s	49.880us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	30.270m	10.494ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.670s	46.773us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	4.590s	155.319us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	4.590s	155.319us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.640s	20.485us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	59.625us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	21.171us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.760s	27.031us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.640s	20.485us	1	1	100.00
		sram_ctrl_csr_rw	1.620s	59.625us	1	1	100.00
		sram_ctrl_csr_aliasing	1.770s	21.171us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.760s	27.031us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.610s	2.170ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
		sram_ctrl_tl_intg_err	2.290s	431.252us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.290s	431.252us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	35.590s	2.215ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	35.590s	2.215ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.620s	59.625us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	4.616m	10.220ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	4.616m	10.220ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	4.616m	10.220ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	11.560s	14.479ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.790s	36.353us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.610s	2.170ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	2.170s	43.505us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	26.370s	501.901us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	26.370s	501.901us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	4.616m	10.220ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	11.560s	14.479ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	26.370s	501.901us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.500s	12.472us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	2.094m	2.157ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.76385138086444411096017924799879836822782979566281383984883856068843051670024
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  43505274 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x3a) != exp (0x6f)
        UVM_INFO @  43505274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending 'pend_req[d2h.d_source].pend' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.61981812077002216440172347233011698516081212003784508634132958541723513105109
      Line 98, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending 'pend_req[d2h.d_source].pend'
        UVM_ERROR @  12472267 ps: (tlul_assert.sv:276) [ASSERT FAILED] respMustHaveReq_A
        UVM_INFO @  12472267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---