UART Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: 7592556

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	5.460s	5.374ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.460s	11.995us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.550s	12.591us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.670s	173.236us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.580s	38.479us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.450s	16.417us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.550s	12.591us	1	1	100.00
		uart_csr_aliasing	1.580s	38.479us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.071m	55.193ms	1	1	100.00
V2	parity	uart_smoke	5.460s	5.374ms	1	1	100.00
		uart_tx_rx	1.071m	55.193ms	1	1	100.00
V2	parity_error	uart_intr	1.300m	120.792ms	1	1	100.00
		uart_rx_parity_err	35.860s	214.458ms	1	1	100.00
V2	watermark	uart_tx_rx	1.071m	55.193ms	1	1	100.00
		uart_intr	1.300m	120.792ms	1	1	100.00
V2	fifo_full	uart_fifo_full	49.980s	39.382ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	3.895m	233.201ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	11.030s	26.828ms	1	1	100.00
V2	rx_frame_err	uart_intr	1.300m	120.792ms	1	1	100.00
V2	rx_break_err	uart_intr	1.300m	120.792ms	1	1	100.00
V2	rx_timeout	uart_intr	1.300m	120.792ms	1	1	100.00
V2	perf	uart_perf	14.317m	21.917ms	1	1	100.00
V2	sys_loopback	uart_loopback	9.660s	8.319ms	1	1	100.00
V2	line_loopback	uart_loopback	9.660s	8.319ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.680s	943.147us	1	1	100.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	1.025m	54.537ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.560s	630.661us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	9.870s	6.300ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	6.315m	184.977ms	1	1	100.00
V2	stress_all	uart_stress_all	42.310s	176.767ms	0	1	0.00
V2	alert_test	uart_alert_test	1.590s	13.389us	1	1	100.00
V2	intr_test	uart_intr_test	1.410s	29.791us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.230s	32.364us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.230s	32.364us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.460s	11.995us	1	1	100.00
		uart_csr_rw	1.550s	12.591us	1	1	100.00
		uart_csr_aliasing	1.580s	38.479us	1	1	100.00
		uart_same_csr_outstanding	1.570s	18.205us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.460s	11.995us	1	1	100.00
		uart_csr_rw	1.550s	12.591us	1	1	100.00
		uart_csr_aliasing	1.580s	38.479us	1	1	100.00
		uart_same_csr_outstanding	1.570s	18.205us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	2.000s	113.905us	1	1	100.00
		uart_tl_intg_err	2.020s	179.249us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	2.020s	179.249us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	19.130s	12.078ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:
  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.66698418130762976108679481822131360446396404481293090341386072660873280690364
      Line 119, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 176712477504 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 176712948096 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 176712948096 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 176725183488 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 176725183488 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0