CHIP Simulation Results

Thursday June 05 2025 17:03:55 UTC

GitHub Revision: `7592556`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	2.770m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	2.770m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.548m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.656m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	1.651m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.856m	5.091ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.856m	5.091ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.856m	5.091ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	26.780s	10.160us	0	1	0.00
		chip_sw_example_manufacturer	2.758m		0	1	0.00
		chip_sw_example_concurrency	3.287m	3.177ms	1	1	100.00
		chip_sw_uart_smoketest_signed	14.304s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.390s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	10.380s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	10.380s		0	1	0.00
V1	xbar_smoke	xbar_smoke	11.010s	12.502us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	2.730m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	10.172m	8.358ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.821m	5.914ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	1.168m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	56.716s		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	1.449m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	1.077m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.340s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.340s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	2.716m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	2.583m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	2.986m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	2.986m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	2.544m	4.033ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.736m	5.521ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	4.783m	14.206ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	11.774s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.480s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	12.755m	20.794ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.268m	6.090ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.706m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.706m	18.019ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	11.318s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.894ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.894ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	6.819m	18.017ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.582m	5.370ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.170m	5.369ms	1	1	100.00
		chip_sw_aes_idle	4.327m	4.728ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.600m	3.398ms	1	1	100.00
		chip_sw_kmac_idle	4.200m	3.482ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	13.188m	12.014ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.782m	12.025ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	12.541m	12.017ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	12.489m	12.014ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.930s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.737s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.795s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.443s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.930s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.737s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.795s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.443s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.627s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.240s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.730s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.400s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.360s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.664s		0	1	0.00
		chip_sw_clkmgr_jitter	4.219m	5.165ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.150m	5.571ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	12.705s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	38.270s	10.300us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	34.080s	10.160us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	33.930s	10.300us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	42.060s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	34.350s	10.180us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	13.187s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	10.582s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	14.142s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	11.237s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.921m	9.951ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.731m	4.894ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	17.627s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.921m	9.951ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	12.261s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	12.669s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	15.697s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.707s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	13.851s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	4.783m	14.206ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.306m	20.023ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.388m	9.757ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	8.626m	7.130ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.237m	3.916ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	10.753s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.686s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	12.601s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	8.626m	7.130ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	10.711s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.637s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	10.900s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	10.630s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	10.587s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	10.793s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.686s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.091s		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.853m	6.677ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.973s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.827s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.836s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.393s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.610m	8.186ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	9.099m	11.432ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.392s		0	1	0.00
		chip_prim_tl_access	14.322m	17.012ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.580s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	16.601s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.930s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	14.737s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	10.795s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.608s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.443s		0	1	0.00
		chip_rv_dm_lc_disabled	12.755m	20.794ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	3.758m	4.129ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	48.240s	10.320us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.266m	3.978ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.327m	4.728ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.660m	4.983ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	34.730s	10.180us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.600m	3.398ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.831m	3.141ms	1	1	100.00
		chip_sw_kmac_mode_kmac	5.572m	5.401ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	35.360s	10.180us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.610m	8.186ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.640s	10.200us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.737m	4.327ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.200m	3.482ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.337s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.337s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	13.054s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.800m	4.673ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	10.706s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.610m	8.186ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.400s	10.360us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	15.158s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	10.627s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.170m	5.369ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.170m	5.369ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.170m	5.369ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.347m	6.356ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.099m	11.432ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.099m	11.432ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	9.112m	7.428ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.664s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.392s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
		chip_sw_data_integrity_escalation	2.986m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.347m	6.356ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.610m	8.186ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.112m	7.428ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.356m	4.792ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.347m	6.356ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.610m	8.186ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	9.112m	7.428ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.356m	4.792ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.632s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	22.091s		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	25.973s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	16.827s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	13.836s		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	15.393s		0	1	0.00
		chip_sw_lc_ctrl_transition	13.816s		0	1	0.00
		chip_prim_tl_access	14.322m	17.012ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	14.322m	17.012ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	13.067s		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	12.293s		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	10.582s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	10.627s		0	1	0.00
		chip_sw_aes_enc_jitter_en	48.240s	10.320us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	34.730s	10.180us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	39.400s	10.360us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	35.360s	10.180us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.664s		0	1	0.00
		chip_sw_clkmgr_jitter	4.219m	5.165ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	6.138m	5.526ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	6.138m	5.526ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.219m	3.944ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.226m	4.434ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	3.776m	3.831ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	6.216m	4.858ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	3.950m	5.479ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.899m	4.535ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.356m	4.792ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.306m	20.023ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.306m	20.023ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.810m	5.339ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.504m	6.200ms	1	1	100.00
		chip_sw_clkmgr_smoketest	2.923m	5.437ms	1	1	100.00
		chip_sw_csrng_smoketest	3.427m	4.119ms	1	1	100.00
		chip_sw_gpio_smoketest	3.673m	3.919ms	1	1	100.00
		chip_sw_hmac_smoketest	4.642m	5.329ms	1	1	100.00
		chip_sw_kmac_smoketest	3.785m	3.989ms	1	1	100.00
		chip_sw_otbn_smoketest	4.196m	5.676ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.522m	4.569ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.828m	3.922ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.212m	6.655ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.751m	4.673ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.452m	3.597ms	1	1	100.00
		chip_sw_uart_smoketest	3.140m	5.152ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	13.518s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	14.304s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	2.730m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	10.938s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	3.644m	4.240ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.986m	5.743ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.716m	5.451ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.588m	5.350ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	13.567s		0	1	0.00
		chip_rv_dm_lc_disabled	12.755m	20.794ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	11.141s		0	1	0.00
		chip_sw_lc_walkthrough_prod	15.937s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	11.341s		0	1	0.00
		chip_sw_lc_walkthrough_rma	1.214m		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	13.567s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	17.708s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	11.397s		0	1	0.00
		rom_volatile_raw_unlock	10.852s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.232s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	1.999m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	2.326m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.484m	2.959ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.484m	2.959ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	10.380s		0	1	0.00
		chip_same_csr_outstanding	10.150s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	10.380s		0	1	0.00
		chip_same_csr_outstanding	10.150s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	1.172m	59.098us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.820s	12.482us	1	1	100.00
		xbar_smoke_large_delays	4.631m	2.497ms	1	1	100.00
		xbar_smoke_slow_rsp	5.423m	2.135ms	1	1	100.00
		xbar_random_zero_delays	1.301m	75.035us	1	1	100.00
		xbar_random_large_delays	20.079m	10.514ms	1	1	100.00
		xbar_random_slow_rsp	26.053m	10.039ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	34.020s	23.513us	1	1	100.00
		xbar_error_and_unmapped_addr	27.700s	60.003us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	42.010s	42.069us	1	1	100.00
		xbar_error_and_unmapped_addr	27.700s	60.003us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	1.150m	75.484us	1	1	100.00
		xbar_access_same_device_slow_rsp	22.975m	8.418ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	2.056m	380.488us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	9.789m	527.608us	1	1	100.00
		xbar_stress_all_with_error	2.001m	128.706us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.679m	415.614us	1	1	100.00
		xbar_stress_all_with_reset_error	6.290s	6.933us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	14.680s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	12.231s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	12.238s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	11.820s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	12.001s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	12.395s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	13.522s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.983s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	11.806s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.589s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	12.124s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	10.880s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.555s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.196s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.986s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.354s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.619s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	11.839s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.746s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	11.364s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.368s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	11.611s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	11.983s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.899s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	13.231s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.040s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.729s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.632s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.031s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	13.878s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.000s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	12.017s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.211s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	11.223s		0	1	0.00
		rom_e2e_asm_init_dev	11.805s		0	1	0.00
		rom_e2e_asm_init_prod	11.030s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.485s		0	1	0.00
		rom_e2e_asm_init_rma	10.605s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	10.305s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	10.331s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.382s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.584s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.522m	5.551ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.618m	5.406ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.001s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.568s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.557s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.123s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.305m	12.693ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	41.092s		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	17.374m	16.528ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.056s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.288s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.001s		0	1	0.00
		rom_e2e_jtag_debug_dev	10.568s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.557s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.558s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.513s		0	1	0.00
		rom_e2e_jtag_inject_rma	10.256s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	46.656s		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.001m	12.551ms	1	1	100.00
		chip_plic_all_irqs_0	9.509m	5.775ms	1	1	100.00
		chip_plic_all_irqs_10	10.439m	7.211ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.695m	4.499ms	1	1	100.00
		chip_sw_dma_abort	3.683m	3.292ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	10.486s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	10.718s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.386s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.613s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.614s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.474s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.576s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.320s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.568s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	10.880s		0	1	0.00
		chip_sw_mbx_smoketest	3.904m	4.907ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.111342463049208798334295495848876628721857920422292601084373518657631899449384
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (ce4392)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 147.350s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.93383221951504641879057665318743613032664618729685246174681071927431537195029
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (e5935a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 168.195s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.111202374228467490451100820629595050816637233948089589632611187175222695622272
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (bf3683)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 151.306s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.33517876662792328806835886528216556397412334000392041986571835588657012888053
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (10b5b1)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 144.796s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.61493279572748091875431713237185805272156559548240306498081790331008857435582
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (7822a0)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 156.203s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.36974538307319656949334363075506018743938758573836468133915161725404636560284
    Line 426, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.320001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.102672403782887461523233221116117212641764180292795626876213755958142536183446
    Line 428, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.92600411225072852594787296535795578430630529403619864801699173065491122337269
    Line 429, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.360001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.46188784890133799771851839027647955501172234464606322754425898469706173477530
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.25820594078149853337168963536969067023016582554989616363097051336020224581650
    Line 414, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.300001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.10125723261062633063869611032978585544072259633494827102592028715767847186413
Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12014.475199 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.475199 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.34071262248085158404860918880408802570568406521178416162040095467817450865476
Line 442, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12024.761637 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12024.761637 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.36570244203175082125201264824692830325645508691571945422741492634741329634432
Line 437, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12016.788377 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12016.788377 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.61998961847300863581698416364046264270339349334719584939887825802105040169110
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.412643 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.412643 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.107115734466396497863743651063189993294653469674978903468489204051762628662802
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.72715155932894730248143425703690562156634730108009243116192459671413086281291
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.34567166157230459200817093955645662904789741146769991677129798030894592281522
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.7557647703333905772592047619253081748908461866943011086597821234852810875436
Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20022.716818 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20022.716818 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.43127710739622214795615240724001771667230576145981264916869945826295111996038
Line 480, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18018.880440 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18018.880440 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.63912332054160657696460255013963937448402296468285983120997979237600276973808
Line 482, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18016.897591 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.897591 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.1857335438891411419228499248716863302016312105375371418798841317346928779495
Line 483, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 8185.993944 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (12894656130400049491884029724296985897373335506174662043351092166227247321650 [0x1c821de24c7d95d48cb2a0475ab56ad815a4753094c8322454a9b90d70595232] vs 98833692491202318933471621846574948364037531434450225910658951158968980813018 [0xda81e338d5cd9b597faf59bf3c040fecdc63fe417aea9b970f1d414563cf34da])
  UVM_INFO @ 8185.993944 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.65372354445483991128401235327759322711007419865467851549091996287749357715803
Line 476, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6676.858544 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (28607170832125744050448226925243255940463295211498011498754947745721439297108 [0x3f3f15bc0af9458dc4fbcddb96c9955b778e3ba52db257f2fc74c6fe6a911e54] vs 27198654705352447599948566715809316363739432836812148977091798401834127086631 [0x3c21e49d3c33e31a566a86573fcf4d23bf8cb6b918957373e7874f5a04565427])
  UVM_INFO @ 6676.858544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.58210744735499943878273232289366288444767658680567122607042743674062307014151
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4033.440397 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h579b6f30  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h11  a_opcode: 'h0  a_user: 'h26940  d_param: 'h0  d_source: 'h11  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4033.440397 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.67184887997847116392049269842116130832200467611215597530344405863429904828147
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 5521.208858 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h4d2cb922  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h0  a_user: 'h26932  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 5521.208858 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.6335801815278873725528965004268549299506424496367402196556038434661438991267
    Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.28093450483516022425732379240147950067991102130008832331403245263849843989624
    Line 580, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5914.154928 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5914.154928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.63418462097917377697343049374636208177162795641644576679869595633814907123752
    Line 714, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 7129.930956 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 7129.930956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.40389666943446196842576928493508421061921028981644582212983935254896206370821
    Line 501, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3944.032408 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3944.032408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.33615230646345860672630773534586097518444063951917355375928949102783796245134
    Line 492, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4433.832680 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4433.832680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.30066260165369771488626706779649571134704843820055505417360370854437379397685
    Line 456, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4894.296160 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4894.296160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.79687007274004568868852076463964565949134495369064100278566893537540799022947
    Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 4857.879406 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 4857.879406 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.29960863791869777944239661662239688317896157057270730435105998159778800352472
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36254) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.67366814794359866006113649578497315688940411559245656023012011513615809009961
Line 254, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2958.780460 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_soc_mbx_reg_block, TL item: req: (cip_tl_seq_item@36254) { a_addr: 'h1496010  a_data: 'h6d6d8482  a_mask: 'h1  a_size: 'h1  a_param: 'h0  a_source: 'h90  a_opcode: 'h4  a_user: 'h247cf  d_param: 'h0  d_source: 'h90  d_data: 'h0  d_size: 'h1  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'h12a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 1, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2958.780460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.33301038947527415664718893275176862802737151679900045569580350958144896518017
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 14206.094128 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 14206.094128 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.51755061449671783807746679183159614934762337390739413458101309492182572997050
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.10549422818356673217338635651256183233091516981863501373514991901750411171274
    Line 422, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3292.333296 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3292.333296 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```