DMA Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	281.701us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	312.143us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	3.749ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	18.845us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	69.558us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	10.000s	2.081ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	9.000s	993.508us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	79.897us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	69.558us	1	1	100.00
		dma_csr_aliasing	9.000s	993.508us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	48.000s	28.865ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	3.683m	44.443ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	4.450m	102.415ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	27.900m	1.796s	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	3.683m	44.443ms	1	1	100.00
V2	dma_abort	dma_abort	17.000s	2.994ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.517m	6.713ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	28.343us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	95.451us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	95.451us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	18.845us	1	1	100.00
		dma_csr_rw	4.000s	69.558us	1	1	100.00
		dma_csr_aliasing	9.000s	993.508us	1	1	100.00
		dma_same_csr_outstanding	5.000s	94.210us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	18.845us	1	1	100.00
		dma_csr_rw	4.000s	69.558us	1	1	100.00
		dma_csr_aliasing	9.000s	993.508us	1	1	100.00
		dma_same_csr_outstanding	5.000s	94.210us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	717.294us	1	1	100.00
		dma_generic_stress	27.900m	1.796s	1	1	100.00
		dma_handshake_stress	3.683m	44.443ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	6.000s	3.466ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.417m	4.846ms	1	1	100.00
		dma_longer_transfer	7.000s	552.545us	1	1	100.00
		TOTAL			21	21	100.00