HMAC Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 9.490s 980.090us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.480s 51.922us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.850s 530.347us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 8.200s 1.909ms 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 2.990s 109.744us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 7.763m 131.623ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.850s 530.347us 1 1 100.00
hmac_csr_aliasing 2.990s 109.744us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 12.920s 19.079ms 1 1 100.00
V2 back_pressure hmac_back_pressure 54.040s 1.350ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 2.738m 5.109ms 1 1 100.00
hmac_test_sha384_vectors 5.661m 11.353ms 1 1 100.00
hmac_test_sha512_vectors 6.329m 11.546ms 1 1 100.00
hmac_test_hmac256_vectors 7.340s 933.615us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 263.994us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.360ms 1 1 100.00
V2 burst_wr hmac_burst_wr 12.980s 1.284ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 1.257m 914.933us 1 1 100.00
V2 error hmac_error 48.190s 2.263ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 55.350s 18.141ms 1 1 100.00
V2 save_and_restore hmac_smoke 9.490s 980.090us 1 1 100.00
hmac_long_msg 12.920s 19.079ms 1 1 100.00
hmac_back_pressure 54.040s 1.350ms 1 1 100.00
hmac_datapath_stress 1.257m 914.933us 1 1 100.00
hmac_burst_wr 12.980s 1.284ms 1 1 100.00
hmac_stress_all 3.830m 27.020ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 9.490s 980.090us 1 1 100.00
hmac_long_msg 12.920s 19.079ms 1 1 100.00
hmac_back_pressure 54.040s 1.350ms 1 1 100.00
hmac_datapath_stress 1.257m 914.933us 1 1 100.00
hmac_wipe_secret 55.350s 18.141ms 1 1 100.00
hmac_test_sha256_vectors 2.738m 5.109ms 1 1 100.00
hmac_test_sha384_vectors 5.661m 11.353ms 1 1 100.00
hmac_test_sha512_vectors 6.329m 11.546ms 1 1 100.00
hmac_test_hmac256_vectors 7.340s 933.615us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 263.994us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.360ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 9.490s 980.090us 1 1 100.00
hmac_long_msg 12.920s 19.079ms 1 1 100.00
hmac_back_pressure 54.040s 1.350ms 1 1 100.00
hmac_datapath_stress 1.257m 914.933us 1 1 100.00
hmac_burst_wr 12.980s 1.284ms 1 1 100.00
hmac_error 48.190s 2.263ms 1 1 100.00
hmac_wipe_secret 55.350s 18.141ms 1 1 100.00
hmac_test_sha256_vectors 2.738m 5.109ms 1 1 100.00
hmac_test_sha384_vectors 5.661m 11.353ms 1 1 100.00
hmac_test_sha512_vectors 6.329m 11.546ms 1 1 100.00
hmac_test_hmac256_vectors 7.340s 933.615us 1 1 100.00
hmac_test_hmac384_vectors 8.640s 263.994us 1 1 100.00
hmac_test_hmac512_vectors 10.670s 1.360ms 1 1 100.00
hmac_stress_all 3.830m 27.020ms 1 1 100.00
V2 stress_all hmac_stress_all 3.830m 27.020ms 1 1 100.00
V2 alert_test hmac_alert_test 1.490s 17.170us 1 1 100.00
V2 intr_test hmac_intr_test 1.470s 11.786us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.810s 582.374us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.810s 582.374us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.480s 51.922us 1 1 100.00
hmac_csr_rw 1.850s 530.347us 1 1 100.00
hmac_csr_aliasing 2.990s 109.744us 1 1 100.00
hmac_same_csr_outstanding 2.160s 120.855us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.480s 51.922us 1 1 100.00
hmac_csr_rw 1.850s 530.347us 1 1 100.00
hmac_csr_aliasing 2.990s 109.744us 1 1 100.00
hmac_same_csr_outstanding 2.160s 120.855us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.870s 199.463us 1 1 100.00
hmac_tl_intg_err 4.090s 288.808us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 4.090s 288.808us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 9.490s 980.090us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.360s 162.661us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 2.409m 17.818ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 1.820s 9.963us 1 1 100.00
TOTAL 28 28 100.00