I2C Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	16.380s	6.279ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	17.400s	3.313ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.550s	35.137us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.580s	19.020us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	2.740s	117.090us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.180s	71.086us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	2.030s	69.343us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.580s	19.020us	1	1	100.00
		i2c_csr_aliasing	2.180s	71.086us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.680s	136.933us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	1.112m	18.532ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	20.620s	3.035ms	1	1	100.00
V2	host_override	i2c_host_override	1.590s	35.303us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	1.123m	17.978ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	26.580s	2.807ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.790s	66.688us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.890s	1.219ms	1	1	100.00
		i2c_host_fifo_reset_rx	3.850s	638.703us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	48.170s	21.018ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	7.730s	2.758ms	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.820s	456.796us	0	1	0.00
V2	target_glitch	i2c_target_glitch	6.990s	5.002ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	19.300m	59.666ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	3.460s	944.326us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	10.400s	900.558us	1	1	100.00
		i2c_target_intr_smoke	4.430s	1.552ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.790s	398.073us	1	1	100.00
		i2c_target_fifo_reset_tx	2.110s	443.484us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	7.172m	47.000ms	1	1	100.00
		i2c_target_stress_rd	10.400s	900.558us	1	1	100.00
		i2c_target_intr_stress_wr	8.560s	5.746ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.240s	14.129ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	13.860s	2.000ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.530s	714.257us	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	3.080s	3.549ms	1	1	100.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.530s	393.457us	1	1	100.00
		i2c_target_fifo_watermarks_tx	1.900s	1.291ms	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	20.620s	3.035ms	1	1	100.00
		i2c_host_perf_precise	1.730s	105.262us	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	7.730s	2.758ms	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	4.800s	425.380us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	2.540s	2.614ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.560s	901.375us	1	1	100.00
		i2c_target_nack_txstretch	2.110s	206.845us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.640s	365.967us	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.800s	460.462us	1	1	100.00
V2	alert_test	i2c_alert_test	1.520s	16.125us	1	1	100.00
V2	intr_test	i2c_intr_test	1.580s	18.842us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.760s	115.230us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.760s	115.230us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.550s	35.137us	1	1	100.00
		i2c_csr_rw	1.580s	19.020us	1	1	100.00
		i2c_csr_aliasing	2.180s	71.086us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	20.834us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.550s	35.137us	1	1	100.00
		i2c_csr_rw	1.580s	19.020us	1	1	100.00
		i2c_csr_aliasing	2.180s	71.086us	1	1	100.00
		i2c_same_csr_outstanding	1.670s	20.834us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.610s	490.827us	1	1	100.00
		i2c_sec_cm	2.030s	79.304us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.610s	490.827us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	17.060s	463.038us	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.120s	645.749us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	22.770s	915.250us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.55355720134711800679955655354626679988986818917936575843058128223371635435806
      Line 180, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 18531581389 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @562410
      

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.33613400211626697515900326262680395130818194883136763261238656157189632928638
      Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        UVM_ERROR @ 456796411 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @39399
      

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.75182405060952807930360580643028320175011772075921851651761944594749777983194
      Line 122, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 463038020 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 463038020 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.98327872617617700493495941916079509164657340816131598401299659254072217343885
      Line 95, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 915249594 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 915249594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.100344788276512910921728950659324945718993026839427586860748082997662286140938
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 645749007 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 211 [0xd3])
        UVM_INFO @ 645749007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.24320939652263645159249764753604105309017897616453076452948746748156139336754
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 206844785 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 206844785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---