KEYMGR_DPE Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	keymgr_dpe_smoke	13.520s	2.825ms	0	1	0.00
V1	csr_hw_reset	keymgr_dpe_csr_hw_reset	1.760s	34.776us	1	1	100.00
V1	csr_rw	keymgr_dpe_csr_rw	1.640s	10.268us	1	1	100.00
V1	csr_bit_bash	keymgr_dpe_csr_bit_bash	3.810s	95.370us	1	1	100.00
V1	csr_aliasing	keymgr_dpe_csr_aliasing	4.330s	115.668us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	keymgr_dpe_csr_mem_rw_with_rand_reset	2.330s	39.650us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	keymgr_dpe_csr_rw	1.640s	10.268us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.330s	115.668us	1	1	100.00
V1		TOTAL			5	6	83.33
V2	intr_test	keymgr_dpe_intr_test	1.470s	7.828us	1	1	100.00
V2	alert_test	keymgr_dpe_alert_test	1.570s	12.453us	1	1	100.00
V2	tl_d_oob_addr_access	keymgr_dpe_tl_errors	3.100s	465.993us	1	1	100.00
V2	tl_d_illegal_access	keymgr_dpe_tl_errors	3.100s	465.993us	1	1	100.00
V2	tl_d_outstanding_access	keymgr_dpe_csr_hw_reset	1.760s	34.776us	1	1	100.00
		keymgr_dpe_csr_rw	1.640s	10.268us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.330s	115.668us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.120s	149.079us	1	1	100.00
V2	tl_d_partial_access	keymgr_dpe_csr_hw_reset	1.760s	34.776us	1	1	100.00
		keymgr_dpe_csr_rw	1.640s	10.268us	1	1	100.00
		keymgr_dpe_csr_aliasing	4.330s	115.668us	1	1	100.00
		keymgr_dpe_same_csr_outstanding	2.120s	149.079us	1	1	100.00
V2		TOTAL			4	4	100.00
V2S	tl_intg_err	keymgr_dpe_sec_cm	10.640s	499.042us	1	1	100.00
		keymgr_dpe_tl_intg_err	4.410s	308.611us	1	1	100.00
V2S	shadow_reg_update_error	keymgr_dpe_shadow_reg_errors	2.660s	143.179us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	keymgr_dpe_shadow_reg_errors	2.660s	143.179us	1	1	100.00
V2S	shadow_reg_storage_error	keymgr_dpe_shadow_reg_errors	2.660s	143.179us	1	1	100.00
V2S	shadowed_reset_glitch	keymgr_dpe_shadow_reg_errors	2.660s	143.179us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	keymgr_dpe_shadow_reg_errors_with_csr_rw	4.660s	771.588us	1	1	100.00
V2S	prim_count_check	keymgr_dpe_sec_cm	10.640s	499.042us	1	1	100.00
V2S	prim_fsm_check	keymgr_dpe_sec_cm	10.640s	499.042us	1	1	100.00
V2S		TOTAL			4	4	100.00
		TOTAL			13	14	92.86

Failure Buckets

• UVM_ERROR (keymgr_dpe_scoreboard.sv:565) scoreboard [scoreboard] After a disable kmac sideload key was not presevedexp * vs. act * has 1 failures:
  • Test keymgr_dpe_smoke has 1 failures.

    • 0.keymgr_dpe_smoke.80761157747368292898817116783461345871036028133453701554309873083539872212167
      Line 2940, in log /nightly/runs/scratch/master/keymgr_dpe-sim-vcs/0.keymgr_dpe_smoke/latest/run.log

        UVM_ERROR @ 2824659982 ps: (keymgr_dpe_scoreboard.sv:565) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] After a disable kmac sideload key was not presevedexp 'h8c0eed3a3c43f9690f803bfaff38431ca566a208e02fa6c8863dd2c7f3e272067de1b74825f8e4fce4ffa9145b5e322da4a4fa6cdae421868ef98049c51256c2 vs. act 'h0
        UVM_INFO @ 2824659982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---