KMAC/MASKED Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	7.510s	2.539ms	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.860s	32.940us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.850s	24.350us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.400s	535.810us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	4.280s	203.290us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.420s	93.357us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.850s	24.350us	1	1	100.00
		kmac_csr_aliasing	4.280s	203.290us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.640s	13.226us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.910s	50.931us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	29.780s	1.693ms	1	1	100.00
V2	burst_write	kmac_burst_write	13.935m	28.543ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	29.367m	350.851ms	1	1	100.00
		kmac_test_vectors_sha3_256	29.849m	325.570ms	1	1	100.00
		kmac_test_vectors_sha3_384	23.831m	334.092ms	1	1	100.00
		kmac_test_vectors_sha3_512	13.487m	40.048ms	1	1	100.00
		kmac_test_vectors_shake_128	3.470m	69.349ms	1	1	100.00
		kmac_test_vectors_shake_256	4.679m	124.586ms	1	1	100.00
		kmac_test_vectors_kmac	3.640s	293.675us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.270s	211.121us	1	1	100.00
V2	sideload	kmac_sideload	1.131m	28.073ms	1	1	100.00
V2	app	kmac_app	4.735m	12.306ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	5.010s	165.969us	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	30.530s	3.703ms	1	1	100.00
V2	error	kmac_error	27.880s	2.852ms	1	1	100.00
V2	key_error	kmac_key_error	9.730s	6.532ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.500s	60.810us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	1.800s	22.898us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.150s	103.215us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	40.540s	6.765ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	3.070s	654.298us	1	1	100.00
V2	stress_all	kmac_stress_all	20.340m	108.657ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.610s	39.526us	1	1	100.00
V2	alert_test	kmac_alert_test	1.890s	173.969us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.230s	272.786us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.230s	272.786us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.860s	32.940us	1	1	100.00
		kmac_csr_rw	1.850s	24.350us	1	1	100.00
		kmac_csr_aliasing	4.280s	203.290us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	314.724us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.860s	32.940us	1	1	100.00
		kmac_csr_rw	1.850s	24.350us	1	1	100.00
		kmac_csr_aliasing	4.280s	203.290us	1	1	100.00
		kmac_same_csr_outstanding	2.440s	314.724us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.390s	78.258us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.390s	78.258us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.390s	78.258us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.390s	78.258us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	2.420s	277.524us	0	1	0.00
V2S	tl_intg_err	kmac_sec_cm	32.440s	4.917ms	1	1	100.00
		kmac_tl_intg_err	2.920s	61.718us	1	1	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	2.920s	61.718us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	3.070s	654.298us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	7.510s	2.539ms	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	1.131m	28.073ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.390s	78.258us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	32.440s	4.917ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	32.440s	4.917ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	32.440s	4.917ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	7.510s	2.539ms	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	3.070s	654.298us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	32.440s	4.917ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	42.770s	2.269ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	7.510s	2.539ms	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	22.450s	4.584ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			39	40	97.50

Failure Buckets

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:
  • Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.

    • 0.kmac_shadow_reg_errors_with_csr_rw.53561367332262170625102676724331134843268403406471866497080307573258766629273
      Line 76, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[49] & 'hffffffff)))'
        UVM_ERROR @ 277524129 ps: (kmac_csr_assert_fpv.sv:560) [ASSERT FAILED] prefix_10_rd_A
        UVM_INFO @ 277524129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---