OTBN Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	12.000s	572.675us	1	1	100.00
V1	single_binary	otbn_single	10.000s	34.694us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	6.000s	41.331us	1	1	100.00
V1	csr_rw	otbn_csr_rw	5.000s	32.686us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	226.497us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	6.000s	75.694us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	11.000s	36.821us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	5.000s	32.686us	1	1	100.00
		otbn_csr_aliasing	6.000s	75.694us	1	1	100.00
V1	mem_walk	otbn_mem_walk	23.000s	1.245ms	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	9.000s	69.945us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	26.000s	220.763us	1	1	100.00
V2	multi_error	otbn_multi_err	41.000s	353.307us	1	1	100.00
V2	back_to_back	otbn_multi	22.300m	8.876ms	1	1	100.00
V2	stress_all	otbn_stress_all	30.000s	500.819us	1	1	100.00
V2	lc_escalation	otbn_escalate	7.000s	186.055us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	7.000s	12.900us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	10.000s	73.107us	1	1	100.00
V2	alert_test	otbn_alert_test	7.000s	16.396us	1	1	100.00
V2	intr_test	otbn_intr_test	6.000s	42.580us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	6.000s	20.052us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	6.000s	20.052us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	6.000s	41.331us	1	1	100.00
		otbn_csr_rw	5.000s	32.686us	1	1	100.00
		otbn_csr_aliasing	6.000s	75.694us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	18.190us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	6.000s	41.331us	1	1	100.00
		otbn_csr_rw	5.000s	32.686us	1	1	100.00
		otbn_csr_aliasing	6.000s	75.694us	1	1	100.00
		otbn_same_csr_outstanding	6.000s	18.190us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	9.000s	55.148us	1	1	100.00
		otbn_dmem_err	8.000s	200.421us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	10.000s	24.813us	1	1	100.00
		otbn_controller_ispr_rdata_err	12.000s	67.470us	1	1	100.00
		otbn_mac_bignum_acc_err	10.000s	242.963us	1	1	100.00
		otbn_urnd_err	13.000s	51.742us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	8.000s	14.125us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	8.000s	55.588us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	8.000s	42.966us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
		otbn_tl_intg_err	18.000s	451.683us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	14.000s	90.406us	1	1	100.00
V2S	prim_fsm_check	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	12.000s	572.675us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	8.000s	200.421us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	9.000s	55.148us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	18.000s	451.683us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	7.000s	186.055us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	9.000s	55.148us	1	1	100.00
		otbn_dmem_err	8.000s	200.421us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	12.900us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	14.125us	1	1	100.00
		otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	9.000s	55.148us	1	1	100.00
		otbn_dmem_err	8.000s	200.421us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	12.900us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	14.125us	1	1	100.00
		otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	7.000s	186.055us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	9.000s	55.148us	1	1	100.00
		otbn_dmem_err	8.000s	200.421us	1	1	100.00
		otbn_zero_state_err_urnd	7.000s	12.900us	1	1	100.00
		otbn_illegal_mem_acc	8.000s	14.125us	1	1	100.00
		otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	10.000s	40.571us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	8.000s	111.987us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	20.000s	284.284us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	20.000s	284.284us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	7.000s	51.437us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	11.000s	100.280us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	66.657us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	14.000s	66.657us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	23.990us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	22.300m	8.876ms	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	7.000s	48.669us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	10.000s	34.694us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	1.533m	1.078ms	1	1	100.00
V2S		TOTAL			20	20	100.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	1.117m	401.366us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			40	41	97.56

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:929) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.57945372321180082794518314452219814964912507888436449040309875374697616037503
      Line 154, in log /nightly/runs/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 401366002 ps: (cip_base_vseq.sv:929) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 401366002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---