ROM_CTRL/32KB Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 6.930s 253.839us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 5.950s 174.131us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 5.090s 169.895us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 4.830s 128.165us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 4.350s 578.137us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.110s 587.717us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 5.090s 169.895us 1 1 100.00
rom_ctrl_csr_aliasing 4.350s 578.137us 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 4.370s 126.083us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 4.730s 300.471us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.210s 433.907us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 12.820s 1.492ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 16.680s 1.037ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 5.180s 168.685us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 6.430s 213.575us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 6.430s 213.575us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 5.950s 174.131us 1 1 100.00
rom_ctrl_csr_rw 5.090s 169.895us 1 1 100.00
rom_ctrl_csr_aliasing 4.350s 578.137us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.620s 293.512us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 5.950s 174.131us 1 1 100.00
rom_ctrl_csr_rw 5.090s 169.895us 1 1 100.00
rom_ctrl_csr_aliasing 4.350s 578.137us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.620s 293.512us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 22.420s 830.374us 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
rom_ctrl_tl_intg_err 24.100s 231.414us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 6.930s 253.839us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 6.930s 253.839us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 6.930s 253.839us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 24.100s 231.414us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
rom_ctrl_kmac_err_chk 16.680s 1.037ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 52.040s 18.639ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 22.420s 830.374us 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 1.486m 791.679us 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.737m 16.370ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00