ROM_CTRL/64KB Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.850s 312.663us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.480s 214.272us 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.690s 214.489us 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 6.690s 208.884us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 5.380s 1.009ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 5.690s 980.871us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.690s 214.489us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 1.009ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 5.770s 906.705us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 7.080s 673.691us 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 8.390s 315.159us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 17.650s 2.245ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 15.520s 569.277us 1 1 100.00
V2 alert_test rom_ctrl_alert_test 7.140s 554.226us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 9.050s 298.215us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 9.050s 298.215us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.480s 214.272us 1 1 100.00
rom_ctrl_csr_rw 6.690s 214.489us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 1.009ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.660s 580.977us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.480s 214.272us 1 1 100.00
rom_ctrl_csr_rw 6.690s 214.489us 1 1 100.00
rom_ctrl_csr_aliasing 5.380s 1.009ms 1 1 100.00
rom_ctrl_same_csr_outstanding 6.660s 580.977us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 35.860s 5.910ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
rom_ctrl_tl_intg_err 1.056m 625.088us 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.850s 312.663us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.850s 312.663us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.850s 312.663us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.056m 625.088us 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
rom_ctrl_kmac_err_chk 15.520s 569.277us 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.324m 4.617ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 35.860s 5.910ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.668m 1.275ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 2.337m 17.475ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00