| V1 |
random |
rv_timer_random |
1.530s |
10.830us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.470s |
54.945us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.490s |
45.085us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
3.320s |
276.921us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.540s |
102.736us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.900s |
55.250us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.490s |
45.085us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.540s |
102.736us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.580s |
169.308us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
1.990s |
2.824ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
3.830m |
1.155s |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
3.830m |
1.155s |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
4.140s |
2.652ms |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.460s |
14.187us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.510s |
25.725us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
1.920s |
172.094us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
1.920s |
172.094us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.470s |
54.945us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.490s |
45.085us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.540s |
102.736us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.420s |
56.463us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.470s |
54.945us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.490s |
45.085us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.540s |
102.736us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.420s |
56.463us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.570s |
515.601us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
1.900s |
145.381us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
1.900s |
145.381us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.410s |
55.847us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.490s |
14.127us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
20.170s |
13.491ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |