SPI_DEVICE/1R1W Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	14.120s	1.478ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.980s	15.065us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.480s	201.125us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	16.850s	356.020us	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	10.910s	2.911ms	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.180s	111.669us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.480s	201.125us	1	1	100.00
		spi_device_csr_aliasing	10.910s	2.911ms	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.610s	12.647us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.120s	18.108us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.820s	37.514us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.860s	10.383us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.620s	7.111us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	2.440s	195.722us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	2.440s	195.722us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	13.130s	14.416ms	1	1	100.00
		spi_device_tpm_sts_read	1.860s	18.798us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	10.340s	9.438ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.630s	1.361ms	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	7.370s	1.327ms	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	7.370s	1.327ms	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.680s	771.819us	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.680s	771.819us	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.680s	771.819us	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.680s	771.819us	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.680s	771.819us	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	5.920s	3.450ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	26.160s	33.034ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	26.160s	33.034ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	26.160s	33.034ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	7.350s	1.070ms	1	1	100.00
		spi_device_read_buffer_direct	3.560s	496.563us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	26.160s	33.034ms	1	1	100.00
		spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	59.840s	11.116ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	4.770s	2.210ms	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	4.770s	2.210ms	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	14.120s	1.478ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	1.497m	25.837ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.498m	96.820ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.570s	31.728us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.680s	13.281us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.090s	193.095us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.090s	193.095us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.980s	15.065us	1	1	100.00
		spi_device_csr_rw	2.480s	201.125us	1	1	100.00
		spi_device_csr_aliasing	10.910s	2.911ms	1	1	100.00
		spi_device_same_csr_outstanding	3.190s	945.366us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.980s	15.065us	1	1	100.00
		spi_device_csr_rw	2.480s	201.125us	1	1	100.00
		spi_device_csr_aliasing	10.910s	2.911ms	1	1	100.00
		spi_device_same_csr_outstanding	3.190s	945.366us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.110s	259.215us	1	1	100.00
		spi_device_tl_intg_err	17.770s	4.668ms	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	17.770s	4.668ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	27.700s	10.272ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.49561027054712878385771365628861388446846103133349990217473202534104076901231
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   8746611 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[62])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   8746611 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   8746611 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[958])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.46406939434400525560721400912469229782940992281835753278789619361678122906468
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   4499975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xe33d7b [111000110011110101111011] vs 0x0 [0])
        UVM_ERROR @   4561975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xed6214 [111011010110001000010100] vs 0x0 [0])
        UVM_ERROR @   4655975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3b5d8b [1110110101110110001011] vs 0x0 [0])
        UVM_ERROR @   4705975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x26b440 [1001101011010001000000] vs 0x0 [0])
        UVM_ERROR @   4730975 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6332f [1100011001100101111] vs 0x0 [0])