SPI_HOST Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	28.000s	5.762ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.066us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	4.000s	17.959us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	359.259us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	5.000s	106.861us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	24.434us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	4.000s	17.959us	1	1	100.00
		spi_host_csr_aliasing	5.000s	106.861us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	17.577us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	4.000s	48.855us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	62.521us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	121.197us	1	1	100.00
		spi_host_error_cmd	4.000s	22.052us	1	1	100.00
		spi_host_event	12.000s	2.079ms	1	1	100.00
V2	clock_rate	spi_host_speed	7.000s	436.760us	1	1	100.00
V2	speed	spi_host_speed	7.000s	436.760us	1	1	100.00
V2	chip_select_timing	spi_host_speed	7.000s	436.760us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	5.000s	55.781us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	51.836us	1	1	100.00
V2	cpol_cpha	spi_host_speed	7.000s	436.760us	1	1	100.00
V2	full_cycle	spi_host_speed	7.000s	436.760us	1	1	100.00
V2	duplex	spi_host_smoke	28.000s	5.762ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	28.000s	5.762ms	1	1	100.00
V2	stress_all	spi_host_stress_all	53.000s	2.753ms	1	1	100.00
V2	spien	spi_host_spien	5.000s	908.702us	1	1	100.00
V2	stall	spi_host_status_stall	34.000s	27.128ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	5.000s	89.629us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	121.197us	1	1	100.00
V2	alert_test	spi_host_alert_test	4.000s	18.689us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	60.033us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	5.000s	278.640us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	5.000s	278.640us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.066us	1	1	100.00
		spi_host_csr_rw	4.000s	17.959us	1	1	100.00
		spi_host_csr_aliasing	5.000s	106.861us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	133.801us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.066us	1	1	100.00
		spi_host_csr_rw	4.000s	17.959us	1	1	100.00
		spi_host_csr_aliasing	5.000s	106.861us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	133.801us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	87.706us	1	1	100.00
		spi_host_sec_cm	4.000s	46.760us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	87.706us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	5.000m	46.911ms	1	1	100.00
		TOTAL			26	26	100.00