SRAM_CTRL/RET Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	2.370s	114.963us	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.560s	51.848us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.480s	19.310us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.020s	96.186us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.650s	26.218us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.030s	104.486us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.480s	19.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	26.218us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	5.850s	1.348ms	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	6.860s	788.961us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	6.071m	8.496ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	5.168m	4.484ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	1.109m	5.188ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	6.849m	2.296ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	2.000s	277.978us	1	1	100.00
V2	executable	sram_ctrl_executable	3.048m	8.109ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	1.259m	4.035ms	1	1	100.00
		sram_ctrl_partial_access_b2b	4.418m	15.986ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	2.360s	147.180us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	34.710s	139.107us	1	1	100.00
		sram_ctrl_throughput_w_readback	15.110s	154.307us	1	1	100.00
V2	regwen	sram_ctrl_regwen	16.672m	3.935ms	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.870s	67.531us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	23.283m	37.362ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.600s	20.147us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.650s	128.358us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.650s	128.358us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.560s	51.848us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	19.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	26.218us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	26.289us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.560s	51.848us	1	1	100.00
		sram_ctrl_csr_rw	1.480s	19.310us	1	1	100.00
		sram_ctrl_csr_aliasing	1.650s	26.218us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.570s	26.289us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	2.710s	895.042us	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
		sram_ctrl_tl_intg_err	2.440s	77.224us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.440s	77.224us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	16.672m	3.935ms	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	16.672m	3.935ms	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.480s	19.310us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	3.048m	8.109ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	3.048m	8.109ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	3.048m	8.109ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	2.000s	277.978us	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.860s	45.171us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	2.710s	895.042us	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.780s	58.816us	1	1	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	2.370s	114.963us	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	2.370s	114.963us	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	3.048m	8.109ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	2.000s	277.978us	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	2.370s	114.963us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.890s	1.473us	0	1	0.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	11.536m	3.742ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			30	31	96.77

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:
  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.69284745345030793955114001982295992787745047702316056197192970069373434514590
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   1473295 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   1473295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---