UART Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: ea3ff74

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	6.240s	6.020ms	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.510s	14.368us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.570s	11.533us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.890s	511.030us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.570s	35.004us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.580s	48.468us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.570s	11.533us	1	1	100.00
		uart_csr_aliasing	1.570s	35.004us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	28.670s	89.670ms	1	1	100.00
V2	parity	uart_smoke	6.240s	6.020ms	1	1	100.00
		uart_tx_rx	28.670s	89.670ms	1	1	100.00
V2	parity_error	uart_intr	19.140s	15.640ms	1	1	100.00
		uart_rx_parity_err	37.520s	23.558ms	1	1	100.00
V2	watermark	uart_tx_rx	28.670s	89.670ms	1	1	100.00
		uart_intr	19.140s	15.640ms	1	1	100.00
V2	fifo_full	uart_fifo_full	18.800s	166.198ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	2.796m	155.669ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	51.500s	94.719ms	1	1	100.00
V2	rx_frame_err	uart_intr	19.140s	15.640ms	1	1	100.00
V2	rx_break_err	uart_intr	19.140s	15.640ms	1	1	100.00
V2	rx_timeout	uart_intr	19.140s	15.640ms	1	1	100.00
V2	perf	uart_perf	7.082m	11.971ms	1	1	100.00
V2	sys_loopback	uart_loopback	2.680s	3.043ms	1	1	100.00
V2	line_loopback	uart_loopback	2.680s	3.043ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	1.750s	9.314us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	4.980s	3.794ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	2.090s	1.123ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	7.610s	6.215ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.724m	106.258ms	1	1	100.00
V2	stress_all	uart_stress_all	11.460s	7.894ms	0	1	0.00
V2	alert_test	uart_alert_test	1.360s	22.069us	1	1	100.00
V2	intr_test	uart_intr_test	1.530s	44.317us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.130s	256.406us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.130s	256.406us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.510s	14.368us	1	1	100.00
		uart_csr_rw	1.570s	11.533us	1	1	100.00
		uart_csr_aliasing	1.570s	35.004us	1	1	100.00
		uart_same_csr_outstanding	1.600s	46.152us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.510s	14.368us	1	1	100.00
		uart_csr_rw	1.570s	11.533us	1	1	100.00
		uart_csr_aliasing	1.570s	35.004us	1	1	100.00
		uart_same_csr_outstanding	1.600s	46.152us	1	1	100.00
V2		TOTAL			16	18	88.89
V2S	tl_intg_err	uart_sec_cm	1.590s	39.313us	1	1	100.00
		uart_tl_intg_err	1.760s	58.010us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.760s	58.010us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	10.840s	7.370ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			24	27	88.89

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 2 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.3623739877268673228002784111378176314971357636277839077569699141154735631765
      Line 69, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @   1814101 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   1967161 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   2120221 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   2273281 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @   2426341 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
      

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.99737115337059172151845537703597572500558265196653697375780392596889338914954
      Line 85, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 4217538955 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_INFO @ 4589077045 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/378
        UVM_ERROR @ 4815846049 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 4815846049 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 4820846044 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all has 1 failures.

    • 0.uart_stress_all.108671213637347352378710811132872164720553398834298077092017151604945891871900
      Line 79, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all/latest/run.log

        UVM_ERROR @ 6898633543 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3,                                 clk_pulses: 0
        UVM_ERROR @ 6898643644 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 6898653745 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
        UVM_ERROR @ 6946542586 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 6946542586 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0