CHIP Simulation Results

Monday June 09 2025 17:09:08 UTC

GitHub Revision: `ea3ff74`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	13.672m		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	13.672m		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	13.218m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	13.026m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	12.826m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.320m	6.076ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.320m	6.076ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.320m	6.076ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	25.900s	10.280us	0	1	0.00
		chip_sw_example_manufacturer	16.110m		0	1	0.00
		chip_sw_example_concurrency	3.890m	3.351ms	1	1	100.00
		chip_sw_uart_smoketest_signed	10.819s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	9.730s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	9.610s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	9.610s		0	1	0.00
V1	xbar_smoke	xbar_smoke	16.720s	54.405us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	14.236m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	12.072m	9.411ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	3.251m	4.244ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	11.466m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	12.408m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	13.326m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.491m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	3.370s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	3.370s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	13.991m		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	13.656m		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	15.040m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	15.040m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.379m	4.934ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.426m	3.433ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.362m	15.604ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.083s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	12.157s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	10.350m	23.859ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.617m	4.467ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	19.705m	18.020ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	19.705m	18.020ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	23.976s		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.350m	4.858ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	4.350m	4.858ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	7.425m	18.016ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	3.327m	5.412ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	5.113m	4.157ms	1	1	100.00
		chip_sw_aes_idle	3.314m	3.304ms	1	1	100.00
		chip_sw_hmac_enc_idle	3.500m	3.387ms	1	1	100.00
		chip_sw_kmac_idle	3.535m	4.792ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	12.134m	12.014ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	11.715m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.565m	12.018ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	11.912m	12.015ms	0	1	0.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	13.227s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.371s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.080s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.994s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.281s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	13.227s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.371s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.080s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.994s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.281s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.452s		0	1	0.00
		chip_sw_aes_enc_jitter_en	33.300s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.110s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.130s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	33.900s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.386s		0	1	0.00
		chip_sw_clkmgr_jitter	4.155m	5.216ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.686m	4.123ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	11.998s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	34.800s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	34.690s	10.340us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	32.870s	10.240us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	33.130s	10.260us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	36.750s	10.100us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.710s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	11.401s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.620s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	13.121s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	10.603m	14.557ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	4.350m	4.858ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	57.961s		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	10.603m	14.557ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	18.629s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1.493m		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	13.614s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	38.902s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	49.582s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.362m	15.604ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	19.715m	20.016ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.374m	6.452ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.891m	6.878ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	3.021m	5.602ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	26.870s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.959s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	26.983s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.891m	6.878ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	13.854s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	12.311s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	20.458s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.952s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.094s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	12.292s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.959s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	10.137m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.373m	6.226ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.622m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	9.658m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.178m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	8.996m		0	1	0.00
		chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.314m	6.010ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	8.776m	10.156ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	13.962s		0	1	0.00
		chip_prim_tl_access	11.605m	25.649ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	13.227s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	14.371s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.166s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.080s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	11.713s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.994s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.281s		0	1	0.00
		chip_rv_dm_lc_disabled	10.350m	23.859ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.758m	6.038ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	33.300s	10.140us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.517m	3.633ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	3.314m	3.304ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	3.703m	5.673ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	35.110s	10.260us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	3.500m	3.387ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.484m	3.186ms	1	1	100.00
		chip_sw_kmac_mode_kmac	3.958m	4.679ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	33.900s	10.380us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.314m	6.010ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	31.600s	10.220us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.626m	4.670ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.535m	4.792ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	13.423s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	13.423s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	59.032s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.010m	4.168ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	19.010s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.314m	6.010ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.130s	10.140us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	29.998s		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	14.452s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	5.113m	4.157ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	5.113m	4.157ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	5.113m	4.157ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.018m	5.710ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.776m	10.156ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.776m	10.156ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.546m	8.950ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.386s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	13.962s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
		chip_sw_data_integrity_escalation	15.040m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.018m	5.710ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.314m	6.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.546m	8.950ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.114m	4.577ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.018m	5.710ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.314m	6.010ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.546m	8.950ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.114m	4.577ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.936s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	10.137m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	9.622m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	9.658m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	9.178m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	8.996m		0	1	0.00
		chip_sw_lc_ctrl_transition	5.947m		0	1	0.00
		chip_prim_tl_access	11.605m	25.649ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	11.605m	25.649ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	7.928m		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	7.636m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	11.401s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	14.452s		0	1	0.00
		chip_sw_aes_enc_jitter_en	33.300s	10.140us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	35.110s	10.260us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	52.130s	10.140us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	33.900s	10.380us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	13.386s		0	1	0.00
		chip_sw_clkmgr_jitter	4.155m	5.216ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	7.499m	8.533ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	7.499m	8.533ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	3.806m	3.839ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	4.095m	5.180ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	2.990m	4.417ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.425m	5.006ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	4.560m	4.169ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.785m	4.959ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	4.114m	4.577ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	19.715m	20.016ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	19.715m	20.016ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.825m	5.199ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.632m	5.670ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.434m	4.769ms	1	1	100.00
		chip_sw_csrng_smoketest	2.846m	5.725ms	1	1	100.00
		chip_sw_gpio_smoketest	2.962m	3.284ms	1	1	100.00
		chip_sw_hmac_smoketest	3.807m	6.237ms	1	1	100.00
		chip_sw_kmac_smoketest	3.728m	3.984ms	1	1	100.00
		chip_sw_otbn_smoketest	4.891m	5.554ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.072m	5.152ms	1	1	100.00
		chip_sw_rv_plic_smoketest	3.561m	5.575ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.260m	5.371ms	1	1	100.00
		chip_sw_rstmgr_smoketest	2.823m	5.636ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.238m	4.585ms	1	1	100.00
		chip_sw_uart_smoketest	3.575m	4.325ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	15.527s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	10.819s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	14.236m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	12.700s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	4.431m	4.854ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.463m	4.488ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.543m	4.493ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.514m	6.149ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	41.107s		0	1	0.00
		chip_rv_dm_lc_disabled	10.350m	23.859ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	5.820m		0	1	0.00
		chip_sw_lc_walkthrough_prod	3.622m		0	1	0.00
		chip_sw_lc_walkthrough_prodend	3.480m		0	1	0.00
		chip_sw_lc_walkthrough_rma	10.449s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	41.107s		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	11.149s		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	16.086s		0	1	0.00
		rom_volatile_raw_unlock	11.331s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	10.766s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	13.302m		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	13.410m		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.885m	4.556ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.885m	4.556ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	9.610s		0	1	0.00
		chip_same_csr_outstanding	13.030s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	9.610s		0	1	0.00
		chip_same_csr_outstanding	13.030s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	3.191m	565.642us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.840s	13.036us	1	1	100.00
		xbar_smoke_large_delays	4.351m	2.440ms	1	1	100.00
		xbar_smoke_slow_rsp	5.496m	2.252ms	1	1	100.00
		xbar_random_zero_delays	53.070s	48.228us	1	1	100.00
		xbar_random_large_delays	6.803m	3.898ms	1	1	100.00
		xbar_random_slow_rsp	11.809m	4.928ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	25.730s	19.410us	1	1	100.00
		xbar_error_and_unmapped_addr	6.570s	7.601us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	15.460s	11.661us	1	1	100.00
		xbar_error_and_unmapped_addr	6.570s	7.601us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	4.478m	782.632us	1	1	100.00
		xbar_access_same_device_slow_rsp	41.077m	16.817ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	9.740s	10.875us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.505m	1.124ms	1	1	100.00
		xbar_stress_all_with_error	4.555m	898.893us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	6.556m	344.661us	1	1	100.00
		xbar_stress_all_with_reset_error	3.196m	256.434us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	10.309s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	10.639s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	10.589s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	10.332s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	11.918s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.954s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.427s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.485s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	12.314s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.048s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	10.599s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	12.221s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.184s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.196s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	12.065s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	12.245s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.815s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	12.246s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	11.207s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.745s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	11.931s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	12.415s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	12.362s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	11.928s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	12.260s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	12.312s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	13.078s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	11.809s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.484s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.585s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	13.871s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.993s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	13.102s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.819s		0	1	0.00
		rom_e2e_asm_init_dev	13.603s		0	1	0.00
		rom_e2e_asm_init_prod	12.151s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.666s		0	1	0.00
		rom_e2e_asm_init_rma	12.275s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.421s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	12.306s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	11.696s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	13.664s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	4.889m	4.557ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	4.231m	5.004ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.965s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.885s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.915s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.478s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	17.278m	14.288ms	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	9.038m		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	15.523m	15.689ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	12.196s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	10.710s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.965s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.885s		0	1	0.00
		rom_e2e_jtag_debug_rma	10.915s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	13.933s		0	1	0.00
		rom_e2e_jtag_inject_dev	12.106s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.340s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.115m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	17.372m	12.930ms	1	1	100.00
		chip_plic_all_irqs_0	9.131m	7.447ms	1	1	100.00
		chip_plic_all_irqs_10	9.223m	6.929ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.650m	4.381ms	1	1	100.00
		chip_sw_dma_abort	3.293m	3.495ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	12.068s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.670s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	10.990s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	10.680s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	10.786s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	11.245s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	13.138s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	12.032s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	10.686s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.327s		0	1	0.00
		chip_sw_mbx_smoketest	3.827m	5.874ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.112406929623444682701838848478694029860231022461573068294956023612465438882330
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (f3f8a5)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 945.516s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.79125517794821948301640534891692027230086675592659649538673929000307513505507
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (12ba5e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 892.326s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.105070132227162076790886475970573552998365699910963065228086683744359332925390
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (6877cd)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 829.484s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.35267035882719082219189701624857090472016240644294745064658799025832536671915
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_retention_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (0dac61)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 809.516s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.108174256625334544444845610255382860243287092410200374398974018410165338657138
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (b6924e)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 810.410s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.16859580859785760961226527956176288610778401758521895454050477766212596305218
    Line 522, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.41639336631683680954334770519717588796582460042270989856044596423294469116405
    Line 505, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.260001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.22477395226710140607282827584042730606810840866821552843009621607858603009377
    Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.29945563618222346979317117496153525125567091050054277715618008351766506975710
    Line 407, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.12015728954989768637372173868438462526944304238924820188457828688203151748902
    Line 431, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 4 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.78690404458814839398655877052579862600395491272888352068995164231934293874856
Line 430, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12014.366632 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.366632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.68669696301403738352096704862088820269807548469831666841055796859526072075630
Line 432, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12021.055906 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.055906 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.48190379969867395302136750485727590514081631778277724766895259452429329290664
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12018.047103 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12018.047103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_otbn_trans has 1 failures.

0.chip_sw_clkmgr_off_otbn_trans.4639313917970961908744667013876778233160717696433159180569160133835080501638
Line 434, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_otbn_trans/latest/run.log

  UVM_ERROR @ 12014.517425 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.517425 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.31376467463132618545905440576235579043254897384180455276163283238798622552394
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.24063844027874786287247055598365050631088733269289550551764083767608465092565
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.5098957573325809184539269298281279169034821413383914953533966781985879132699
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.45892475879452655064402713385566608611102013160802514258108845426995058168831
Line 580, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20016.216526 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20016.216526 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.64505841340478333719810790643956761685312911433917859328872064627438896456679
Line 602, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18020.379682 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18020.379682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.83520887238920025194326386726900073795940363960146751284636577778786847669404
Line 560, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18015.980875 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18015.980875 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.55037823340939212572744218264369405905905167731952082173382682018859586203409
Line 560, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6010.018830 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (12816924233868882328143009783047468514722268329537462988011658323962137807292 [0x1c561f3e02f8f45b15f74e5184b6c9686cd6892882b70c93038eb4c6af2609bc] vs 111306075209370810394515157429533584161141905090176751366165574273434428803698 [0xf615018bc1373f06c3bb7c09bcf70cda8f2aae976279580ddd4c8153da468a72])
  UVM_INFO @ 6010.018830 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.82382909856440520379173217683151594208005866977280875576306328254648664109171
Line 528, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 6226.058216 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (86669525531305937701039490668405185130995292184736173806111759300500503556899 [0xbf9d368bc75fc18657cf8a0d8015de4e143a2454a7f403e456c3f84f8f667323] vs 56740681023488969770634494204056490771207521783906143844104125299503573278879 [0x7d72165e7716422a1aed500394db2f3a40d35c0b883284cb7677191fc824a09f])
  UVM_INFO @ 6226.058216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.79545971840694714704621788779366962681597655743375891086106931319221299047638
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4934.364255 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'ha735e5ba  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2b  a_opcode: 'h1  a_user: 'h248cd  d_param: 'h0  d_source: 'h2b  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4934.364255 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.12309320667040532499761734072788951053127575759752283240205702173913349109087
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3433.469601 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'he552130  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h2  a_opcode: 'h0  a_user: 'h2690c  d_param: 'h0  d_source: 'h2  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3433.469601 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.8604815045029504968958470933793719175381929429437142704938481374845079877412
    Line 521, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.280001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.4280568726348030566161674144939397687443713687050745439244972706847818366407
    Line 478, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 4244.159412 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 4244.159412 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.21023766169168749227308143315400685745302375746972006752416710081687992949449
    Line 842, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 6877.582968 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 6877.582968 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.61036674157342789088380412301319928523823812983779656510339716287245631983204
    Line 561, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 3839.426216 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 3839.426216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.4987414045899321371051528164068527350099173293709324197963735306975946628296
    Line 488, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 5179.864998 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 5179.864998 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.112760002460867846368670065742576750872709487681291054504946585402316031921662
    Line 637, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 4858.221400 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 4858.221400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.91488836199727776588382874394641504951227366506826132358799790453670192334165
    Line 464, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 5005.808908 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 5005.808908 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.111927985526921579546807742290928636253152265985682022543690886663443458591892
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.59151640670239882413180436551861032261185618440569367565519844570029560474467
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 4555.856452 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 4555.856452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.98622926482306025979164039733850355084611393796648171754368740943987676037931
    Line 402, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15604.094942 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15604.094942 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.74701775153714497620825658565727904169042835946001944188732037137166935325765
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 95
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.56893091837270742918605494994325430639930525130305502716654359722290976086041
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 3494.538222 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 3494.538222 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```