DMA Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	8.000s	1.258ms	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	10.000s	811.732us	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	7.000s	392.525us	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	35.062us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	47.528us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	13.000s	2.032ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	7.000s	80.725us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	5.000s	276.935us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	47.528us	1	1	100.00
		dma_csr_aliasing	7.000s	80.725us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	46.000s	8.258ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	2.400m	12.683ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.217m	85.576ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	6.650m	142.515ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	2.400m	12.683ms	1	1	100.00
V2	dma_abort	dma_abort	18.000s	5.004ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	4.500m	86.608ms	1	1	100.00
V2	intr_test	dma_intr_test	4.000s	12.610us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	6.000s	50.003us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	6.000s	50.003us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	35.062us	1	1	100.00
		dma_csr_rw	4.000s	47.528us	1	1	100.00
		dma_csr_aliasing	7.000s	80.725us	1	1	100.00
		dma_same_csr_outstanding	5.000s	231.921us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	35.062us	1	1	100.00
		dma_csr_rw	4.000s	47.528us	1	1	100.00
		dma_csr_aliasing	7.000s	80.725us	1	1	100.00
		dma_same_csr_outstanding	5.000s	231.921us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	18.000s	53.704us	1	1	100.00
		dma_generic_stress	6.650m	142.515ms	1	1	100.00
		dma_handshake_stress	2.400m	12.683ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	1.058ms	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.050m	10.899ms	1	1	100.00
		dma_longer_transfer	6.000s	293.376us	1	1	100.00
		TOTAL			21	21	100.00