EDN Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.760s	14.556us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.990s	14.085us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.760s	50.620us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	2.710s	249.060us	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	2.370s	76.400us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.060s	18.292us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.760s	50.620us	1	1	100.00
		edn_csr_aliasing	2.370s	76.400us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	2.330s	102.190us	1	1	100.00
V2	csrng_commands	edn_genbits	2.330s	102.190us	1	1	100.00
V2	genbits	edn_genbits	2.330s	102.190us	1	1	100.00
V2	interrupts	edn_intr	1.760s	31.933us	1	1	100.00
V2	alerts	edn_alert	2.190s	25.659us	1	1	100.00
V2	errs	edn_err	1.870s	55.741us	1	1	100.00
V2	disable	edn_disable	1.850s	38.771us	1	1	100.00
		edn_disable_auto_req_mode	1.900s	31.810us	1	1	100.00
V2	stress_all	edn_stress_all	4.780s	3.582ms	1	1	100.00
V2	intr_test	edn_intr_test	1.840s	47.968us	1	1	100.00
V2	alert_test	edn_alert_test	1.670s	18.353us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.130s	524.086us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.130s	524.086us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.990s	14.085us	1	1	100.00
		edn_csr_rw	1.760s	50.620us	1	1	100.00
		edn_csr_aliasing	2.370s	76.400us	1	1	100.00
		edn_same_csr_outstanding	2.320s	25.469us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.990s	14.085us	1	1	100.00
		edn_csr_rw	1.760s	50.620us	1	1	100.00
		edn_csr_aliasing	2.370s	76.400us	1	1	100.00
		edn_same_csr_outstanding	2.320s	25.469us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	5.540s	402.053us	1	1	100.00
		edn_tl_intg_err	2.360s	149.821us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.680s	43.769us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	2.190s	25.659us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	5.540s	402.053us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	5.540s	402.053us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	5.540s	402.053us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	5.540s	402.053us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.190s	25.659us	1	1	100.00
		edn_sec_cm	5.540s	402.053us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.190s	25.659us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.360s	149.821us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.215m	5.650ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00