HMAC Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 6.330s 146.539us 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.740s 90.447us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.720s 65.392us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 11.090s 654.412us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 7.170s 563.797us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 7.956m 68.826ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.720s 65.392us 1 1 100.00
hmac_csr_aliasing 7.170s 563.797us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 36.280s 4.810ms 1 1 100.00
V2 back_pressure hmac_back_pressure 47.800s 3.161ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 10.280s 757.549us 1 1 100.00
hmac_test_sha384_vectors 6.982m 111.455ms 1 1 100.00
hmac_test_sha512_vectors 19.490s 381.207us 1 1 100.00
hmac_test_hmac256_vectors 10.020s 275.619us 1 1 100.00
hmac_test_hmac384_vectors 14.360s 3.984ms 1 1 100.00
hmac_test_hmac512_vectors 8.440s 584.510us 1 1 100.00
V2 burst_wr hmac_burst_wr 1.640s 41.231us 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.354m 13.962ms 1 1 100.00
V2 error hmac_error 1.242m 1.735ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 51.450s 3.431ms 1 1 100.00
V2 save_and_restore hmac_smoke 6.330s 146.539us 1 1 100.00
hmac_long_msg 36.280s 4.810ms 1 1 100.00
hmac_back_pressure 47.800s 3.161ms 1 1 100.00
hmac_datapath_stress 6.354m 13.962ms 1 1 100.00
hmac_burst_wr 1.640s 41.231us 1 1 100.00
hmac_stress_all 4.561m 21.496ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 6.330s 146.539us 1 1 100.00
hmac_long_msg 36.280s 4.810ms 1 1 100.00
hmac_back_pressure 47.800s 3.161ms 1 1 100.00
hmac_datapath_stress 6.354m 13.962ms 1 1 100.00
hmac_wipe_secret 51.450s 3.431ms 1 1 100.00
hmac_test_sha256_vectors 10.280s 757.549us 1 1 100.00
hmac_test_sha384_vectors 6.982m 111.455ms 1 1 100.00
hmac_test_sha512_vectors 19.490s 381.207us 1 1 100.00
hmac_test_hmac256_vectors 10.020s 275.619us 1 1 100.00
hmac_test_hmac384_vectors 14.360s 3.984ms 1 1 100.00
hmac_test_hmac512_vectors 8.440s 584.510us 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 6.330s 146.539us 1 1 100.00
hmac_long_msg 36.280s 4.810ms 1 1 100.00
hmac_back_pressure 47.800s 3.161ms 1 1 100.00
hmac_datapath_stress 6.354m 13.962ms 1 1 100.00
hmac_burst_wr 1.640s 41.231us 1 1 100.00
hmac_error 1.242m 1.735ms 1 1 100.00
hmac_wipe_secret 51.450s 3.431ms 1 1 100.00
hmac_test_sha256_vectors 10.280s 757.549us 1 1 100.00
hmac_test_sha384_vectors 6.982m 111.455ms 1 1 100.00
hmac_test_sha512_vectors 19.490s 381.207us 1 1 100.00
hmac_test_hmac256_vectors 10.020s 275.619us 1 1 100.00
hmac_test_hmac384_vectors 14.360s 3.984ms 1 1 100.00
hmac_test_hmac512_vectors 8.440s 584.510us 1 1 100.00
hmac_stress_all 4.561m 21.496ms 1 1 100.00
V2 stress_all hmac_stress_all 4.561m 21.496ms 1 1 100.00
V2 alert_test hmac_alert_test 1.850s 12.763us 1 1 100.00
V2 intr_test hmac_intr_test 1.500s 27.425us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 3.910s 437.494us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 3.910s 437.494us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.740s 90.447us 1 1 100.00
hmac_csr_rw 1.720s 65.392us 1 1 100.00
hmac_csr_aliasing 7.170s 563.797us 1 1 100.00
hmac_same_csr_outstanding 2.710s 173.951us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.740s 90.447us 1 1 100.00
hmac_csr_rw 1.720s 65.392us 1 1 100.00
hmac_csr_aliasing 7.170s 563.797us 1 1 100.00
hmac_same_csr_outstanding 2.710s 173.951us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 1.980s 238.261us 1 1 100.00
hmac_tl_intg_err 3.990s 141.346us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.990s 141.346us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 6.330s 146.539us 1 1 100.00
V3 stress_reset hmac_stress_reset 3.360s 179.336us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 6.310m 13.779ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 3.190s 51.905us 1 1 100.00
TOTAL 28 28 100.00