I2C Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	54.080s	17.341ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	9.470s	1.003ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.440s	29.292us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.570s	35.995us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	4.230s	739.825us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.320s	141.416us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.600s	25.977us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.570s	35.995us	1	1	100.00
		i2c_csr_aliasing	2.320s	141.416us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	2.400s	127.782us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	2.015m	50.313ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	29.379m	26.083ms	1	1	100.00
V2	host_override	i2c_host_override	1.460s	44.421us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.697m	15.456ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.026m	5.471ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.920s	113.545us	1	1	100.00
		i2c_host_fifo_fmt_empty	4.480s	1.019ms	1	1	100.00
		i2c_host_fifo_reset_rx	7.350s	192.081us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	2.496m	5.007ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	30.750s	918.448us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	1.980s	19.608us	0	1	0.00
V2	target_glitch	i2c_target_glitch	7.120s	8.236ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	4.574m	102.059ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.240s	3.105ms	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	10.810s	727.619us	1	1	100.00
		i2c_target_intr_smoke	5.260s	4.916ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	1.800s	211.404us	1	1	100.00
		i2c_target_fifo_reset_tx	2.200s	240.862us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	38.110s	28.236ms	1	1	100.00
		i2c_target_stress_rd	10.810s	727.619us	1	1	100.00
		i2c_target_intr_stress_wr	5.360s	1.724ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.490s	2.009ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	20.230s	3.887ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	6.720s	2.048ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	21.040s	10.205ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	2.770s	745.182us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.210s	522.738us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	29.379m	26.083ms	1	1	100.00
		i2c_host_perf_precise	3.289m	23.151ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	30.750s	918.448us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	3.910s	213.519us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.230s	627.507us	1	1	100.00
		i2c_target_nack_acqfull_addr	2.840s	3.258ms	1	1	100.00
		i2c_target_nack_txstretch	2.140s	255.715us	0	1	0.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	14.990s	1.020ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	2.610s	461.981us	1	1	100.00
V2	alert_test	i2c_alert_test	1.530s	15.413us	1	1	100.00
V2	intr_test	i2c_intr_test	1.420s	17.709us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.490s	112.572us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.490s	112.572us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.440s	29.292us	1	1	100.00
		i2c_csr_rw	1.570s	35.995us	1	1	100.00
		i2c_csr_aliasing	2.320s	141.416us	1	1	100.00
		i2c_same_csr_outstanding	1.550s	34.653us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.440s	29.292us	1	1	100.00
		i2c_csr_rw	1.570s	35.995us	1	1	100.00
		i2c_csr_aliasing	2.320s	141.416us	1	1	100.00
		i2c_same_csr_outstanding	1.550s	34.653us	1	1	100.00
V2		TOTAL			34	38	89.47
V2S	tl_intg_err	i2c_tl_intg_err	2.010s	88.533us	1	1	100.00
		i2c_sec_cm	1.570s	156.306us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.010s	88.533us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	7.410s	5.821ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.610s	863.278us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	4.220s	1.527ms	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			43	50	86.00

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:

  • Test i2c_host_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_host_stress_all_with_rand_reset.96652302333305663582556611244188610384525582927720164399609523342152162943677
      Line 93, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5821495910 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 5821495910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test i2c_target_stress_all_with_rand_reset has 1 failures.

    • 0.i2c_target_stress_all_with_rand_reset.105161351844813964013206800884006498651644790298599900303137542375238832470755
      Line 89, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1527222574 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1527222574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 1 failures:

  • Test i2c_host_stress_all has 1 failures.

    • 0.i2c_host_stress_all.29796994355497120740249868397664889669451975066098701758479891776287987114223
      Line 187, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

        UVM_ERROR @ 50313026580 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
        ----------------------------------------------------
        Name            Type                Size  Value
        ----------------------------------------------------
        mon_dut_item    i2c_item            -     @1403780
      

• UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*]) has 1 failures:

  • Test i2c_target_unexp_stop has 1 failures.

    • 0.i2c_target_unexp_stop.74650749086724607697817482476351005179618441349029791160701383280803372506315
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log

        UVM_ERROR @ 863278266 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
        UVM_INFO @ 863278266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:

  • Test i2c_target_hrst has 1 failures.

    • 0.i2c_target_hrst.15554960703969759619291070693530114217457794819866826961288960911675806263701
      Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log

        UVM_FATAL @ 10205100366 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
        UVM_INFO @ 10205100366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Error-[NOA] Null object access has 1 failures:

  • Test i2c_host_mode_toggle has 1 failures.

    • 0.i2c_host_mode_toggle.74797361972733466581056432056772741071149854424585186449664784156799685872288
      Line 81, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

        Error-[NOA] Null object access
        src/lowrisc_dv_i2c_env_0.1/i2c_reference_model.sv, 584
          The object at dereference depth 0 is being used before it was
          constructed/allocated.
          Please make sure that the object is allocated before using it.
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: i2c_reg_block.target_nack_count reset value: * has 1 failures:

  • Test i2c_target_nack_txstretch has 1 failures.

    • 0.i2c_target_nack_txstretch.62410341134948519139304168345772976104681652468987968182599822150681414695841
      Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_nack_txstretch/latest/run.log

        UVM_ERROR @ 255715425 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1 [0x1] vs 0 [0x0]) Regname: i2c_reg_block.target_nack_count reset value: 0x0
        UVM_INFO @ 255715425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---