| V1 |
smoke |
keymgr_dpe_smoke |
15.230s |
894.907us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.930s |
26.716us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.690s |
11.893us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
6.270s |
382.437us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
2.960s |
168.340us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
2.500s |
73.443us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.690s |
11.893us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.960s |
168.340us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.770s |
33.720us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.980s |
65.002us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.010s |
215.106us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.010s |
215.106us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.930s |
26.716us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.690s |
11.893us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.960s |
168.340us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.000s |
33.892us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.930s |
26.716us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.690s |
11.893us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
2.960s |
168.340us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.000s |
33.892us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
6.140s |
379.726us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.310s |
122.008us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.630s |
122.282us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.630s |
122.282us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.630s |
122.282us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.630s |
122.282us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
5.060s |
436.003us |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
6.140s |
379.726us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
6.140s |
379.726us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |