KMAC/UNMASKED Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	30.500s	857.716us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.880s	37.866us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.730s	63.149us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	6.040s	300.319us	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.820s	280.367us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.760s	78.559us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.730s	63.149us	1	1	100.00
		kmac_csr_aliasing	3.820s	280.367us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.590s	16.754us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.990s	112.464us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	23.257m	56.425ms	1	1	100.00
V2	burst_write	kmac_burst_write	5.540m	12.748ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	24.538m	97.759ms	1	1	100.00
		kmac_test_vectors_sha3_256	16.639m	26.710ms	1	1	100.00
		kmac_test_vectors_sha3_384	17.874m	510.505ms	1	1	100.00
		kmac_test_vectors_sha3_512	10.730s	277.625us	1	1	100.00
		kmac_test_vectors_shake_128	2.038m	13.619ms	1	1	100.00
		kmac_test_vectors_shake_256	21.816m	116.555ms	1	1	100.00
		kmac_test_vectors_kmac	2.220s	118.961us	1	1	100.00
		kmac_test_vectors_kmac_xof	2.560s	65.379us	1	1	100.00
V2	sideload	kmac_sideload	3.261m	49.645ms	1	1	100.00
V2	app	kmac_app	1.280m	58.635ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	56.450s	5.579ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	2.563m	39.593ms	1	1	100.00
V2	error	kmac_error	1.326m	6.397ms	1	1	100.00
V2	key_error	kmac_key_error	4.390s	2.410ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	3.750s	94.892us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	15.800s	312.484us	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	10.470s	903.284us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	40.130s	11.943ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.690s	53.980us	1	1	100.00
V2	stress_all	kmac_stress_all	7.022m	111.463ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.650s	23.146us	1	1	100.00
V2	alert_test	kmac_alert_test	1.600s	16.413us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.000s	253.859us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.000s	253.859us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.880s	37.866us	1	1	100.00
		kmac_csr_rw	1.730s	63.149us	1	1	100.00
		kmac_csr_aliasing	3.820s	280.367us	1	1	100.00
		kmac_same_csr_outstanding	2.560s	440.620us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.880s	37.866us	1	1	100.00
		kmac_csr_rw	1.730s	63.149us	1	1	100.00
		kmac_csr_aliasing	3.820s	280.367us	1	1	100.00
		kmac_same_csr_outstanding	2.560s	440.620us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.120s	172.566us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.120s	172.566us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.120s	172.566us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.120s	172.566us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	4.230s	218.919us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	53.710s	21.151ms	1	1	100.00
		kmac_tl_intg_err	1.520s	39.594us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.520s	39.594us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.690s	53.980us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	30.500s	857.716us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	3.261m	49.645ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.120s	172.566us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	53.710s	21.151ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	53.710s	21.151ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	53.710s	21.151ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	30.500s	857.716us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.690s	53.980us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	53.710s	21.151ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.860m	42.987ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	30.500s	857.716us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.467m	3.698ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.69315726306127776120465688882826449909521409977365917834179924760901548639266
      Line 184, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3698357428 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483680 [0x80000020]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 3698357428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.98352041575204894958434171963338843490583751349184093288783395217676878484494
      Line 82, in log /nightly/runs/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[43] & 'hffffffff)))'
        UVM_ERROR @  39593785 ps: (kmac_csr_assert_fpv.sv:524) [ASSERT FAILED] prefix_4_rd_A
        UVM_INFO @  39593785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---