df6b01c| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | mbx_smoke | mbx_smoke | 53.000s | 939.177us | 1 | 1 | 100.00 |
| V1 | csr_hw_reset | mbx_csr_hw_reset | 4.000s | 49.196us | 1 | 1 | 100.00 |
| V1 | csr_rw | mbx_csr_rw | 4.000s | 17.175us | 1 | 1 | 100.00 |
| V1 | csr_bit_bash | mbx_csr_bit_bash | 4.000s | 218.968us | 1 | 1 | 100.00 |
| V1 | csr_aliasing | mbx_csr_aliasing | 4.000s | 28.105us | 1 | 1 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | mbx_csr_mem_rw_with_rand_reset | 3.000s | 10.821us | 0 | 1 | 0.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | mbx_csr_rw | 4.000s | 17.175us | 1 | 1 | 100.00 |
| mbx_csr_aliasing | 4.000s | 28.105us | 1 | 1 | 100.00 | ||
| V1 | TOTAL | 5 | 6 | 83.33 | |||
| V2 | mbx_stress | mbx_stress | 1.767m | 13.519ms | 1 | 1 | 100.00 |
| mbx_stress_zero_delays | 58.000s | 9.013ms | 1 | 1 | 100.00 | ||
| V2 | mbx_imbx_oob | mbx_imbx_oob | 1.183m | 62.039ms | 1 | 1 | 100.00 |
| V2 | alert_test | mbx_alert_test | 6.000s | 14.597us | 1 | 1 | 100.00 |
| V2 | tl_d_oob_addr_access | mbx_tl_errors | 3.000s | 5.644us | 0 | 1 | 0.00 |
| V2 | tl_d_illegal_access | mbx_tl_errors | 3.000s | 5.644us | 0 | 1 | 0.00 |
| V2 | tl_d_outstanding_access | mbx_csr_hw_reset | 4.000s | 49.196us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 17.175us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 28.105us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 70.147us | 1 | 1 | 100.00 | ||
| V2 | tl_d_partial_access | mbx_csr_hw_reset | 4.000s | 49.196us | 1 | 1 | 100.00 |
| mbx_csr_rw | 4.000s | 17.175us | 1 | 1 | 100.00 | ||
| mbx_csr_aliasing | 4.000s | 28.105us | 1 | 1 | 100.00 | ||
| mbx_same_csr_outstanding | 3.000s | 70.147us | 1 | 1 | 100.00 | ||
| V2 | TOTAL | 5 | 6 | 83.33 | |||
| V2S | tl_intg_err | mbx_sec_cm | 10.000s | 30.898us | 1 | 1 | 100.00 |
| mbx_tl_intg_err | 4.000s | 4.510us | 0 | 1 | 0.00 | ||
| V2S | TOTAL | 1 | 2 | 50.00 | |||
| TOTAL | 11 | 14 | 78.57 |
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = PutPartialData a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 2 failures:
Test mbx_tl_errors has 1 failures.
0.mbx_tl_errors.44240318863727875601765295754255702630396494035344256797984653423310915234051
Line 82, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest/run.log
UVM_ERROR @ 5644283 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x6cbe55e0 a_data = 0x7e032078 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xe7 a_opcode = PutPartialData a_user = 0x1a33a d_data = 0xf49b5c60 d_size = 0x1 d_param = 0x0 d_source = 0xbc d_opcode = AccessAck d_error = 0 d_user = 111001000100 d_sink = 0 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 5644283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test mbx_csr_mem_rw_with_rand_reset has 1 failures.
0.mbx_csr_mem_rw_with_rand_reset.104114644627542461177308610852405228317943323246402863695140783595488716530139
Line 83, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest/run.log
UVM_ERROR @ 10820772 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0xf1f6fe0c a_data = 0xf98cfb5f a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xa8 a_opcode = PutPartialData a_user = 0x1a0a5 d_data = 0xce7a4e5a d_size = 0x0 d_param = 0x0 d_source = 0xbb d_opcode = AccessAck d_error = 0 d_user = 10010001101111 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 10820772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (tl_host_seq.sv:55) sequencer [tl_seq] fail to find matching req for rsp[*]: a_addr = * a_data = * a_mask = * a_size = * a_param = * a_source = * a_opcode = Get a_user = * d_data = * d_size = * d_param = * d_source = * d_opcode = AccessAck d_error = * d_user = * d_sink = * req_abort_after_a_valid_len = * rsp_abort_after_d_valid_len = * req_completed = * rsp_completed = * has 1 failures:
0.mbx_tl_intg_err.66712267782729416857775398602489204480664907932138299149350941799567649882262
Line 88, in log /nightly/runs/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest/run.log
UVM_ERROR @ 4509939 ps: (tl_host_seq.sv:55) uvm_test_top.env.m_tl_agent_mbx_mem_reg_block.sequencer [uvm_test_top.env.virtual_sequencer._item.tl_seq] fail to find matching req for rsp[0]: a_addr = 0x337c8d8c a_data = 0xb5f38564 a_mask = 0xf a_size = 0x2 a_param = 0x0 a_source = 0xdd a_opcode = Get a_user = 0x26743 d_data = 0x6c3f98cc d_size = 0x3 d_param = 0x0 d_source = 0x61 d_opcode = AccessAck d_error = 0 d_user = 1000011000 d_sink = 1 req_abort_after_a_valid_len = 0 rsp_abort_after_d_valid_len = 0 req_completed = 0 rsp_completed = 1
UVM_INFO @ 4509939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---