ROM_CTRL/64KB Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rom_ctrl_smoke 8.000s 550.709us 1 1 100.00
V1 csr_hw_reset rom_ctrl_csr_hw_reset 7.140s 1.230ms 1 1 100.00
V1 csr_rw rom_ctrl_csr_rw 6.840s 1.067ms 1 1 100.00
V1 csr_bit_bash rom_ctrl_csr_bit_bash 8.260s 216.123us 1 1 100.00
V1 csr_aliasing rom_ctrl_csr_aliasing 9.090s 1.071ms 1 1 100.00
V1 csr_mem_rw_with_rand_reset rom_ctrl_csr_mem_rw_with_rand_reset 6.950s 1.034ms 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr rom_ctrl_csr_rw 6.840s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 1.071ms 1 1 100.00
V1 mem_walk rom_ctrl_mem_walk 7.640s 591.319us 1 1 100.00
V1 mem_partial_access rom_ctrl_mem_partial_access 6.450s 1.025ms 1 1 100.00
V1 TOTAL 8 8 100.00
V2 max_throughput_chk rom_ctrl_max_throughput_chk 6.910s 756.574us 1 1 100.00
V2 stress_all rom_ctrl_stress_all 32.910s 1.125ms 1 1 100.00
V2 kmac_err_chk rom_ctrl_kmac_err_chk 13.620s 1.642ms 1 1 100.00
V2 alert_test rom_ctrl_alert_test 6.530s 370.315us 1 1 100.00
V2 tl_d_oob_addr_access rom_ctrl_tl_errors 8.010s 212.634us 1 1 100.00
V2 tl_d_illegal_access rom_ctrl_tl_errors 8.010s 212.634us 1 1 100.00
V2 tl_d_outstanding_access rom_ctrl_csr_hw_reset 7.140s 1.230ms 1 1 100.00
rom_ctrl_csr_rw 6.840s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 1.071ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.100s 616.593us 1 1 100.00
V2 tl_d_partial_access rom_ctrl_csr_hw_reset 7.140s 1.230ms 1 1 100.00
rom_ctrl_csr_rw 6.840s 1.067ms 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 1.071ms 1 1 100.00
rom_ctrl_same_csr_outstanding 8.100s 616.593us 1 1 100.00
V2 TOTAL 6 6 100.00
V2S corrupt_sig_fatal_chk rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S passthru_mem_tl_intg_err rom_ctrl_passthru_mem_tl_intg_err 38.700s 3.203ms 1 1 100.00
V2S tl_intg_err rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
rom_ctrl_tl_intg_err 1.041m 1.722ms 1 1 100.00
V2S prim_fsm_check rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
V2S prim_count_check rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
V2S sec_cm_checker_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_checker_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_checker_fsm_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_compare_ctrl_flow_consistency rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_compare_ctr_consistency rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_compare_ctr_redun rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
V2S sec_cm_fsm_sparse rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
V2S sec_cm_mem_scramble rom_ctrl_smoke 8.000s 550.709us 1 1 100.00
V2S sec_cm_mem_digest rom_ctrl_smoke 8.000s 550.709us 1 1 100.00
V2S sec_cm_intersig_mubi rom_ctrl_smoke 8.000s 550.709us 1 1 100.00
V2S sec_cm_bus_integrity rom_ctrl_tl_intg_err 1.041m 1.722ms 1 1 100.00
V2S sec_cm_bus_local_esc rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
rom_ctrl_kmac_err_chk 13.620s 1.642ms 1 1 100.00
V2S sec_cm_mux_mubi rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_mux_consistency rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_ctrl_redun rom_ctrl_corrupt_sig_fatal_chk 1.206m 3.870ms 1 1 100.00
V2S sec_cm_ctrl_mem_integrity rom_ctrl_passthru_mem_tl_intg_err 38.700s 3.203ms 1 1 100.00
V2S sec_cm_tlul_fifo_ctr_redun rom_ctrl_sec_cm 4.624m 4.763ms 1 1 100.00
V2S TOTAL 4 4 100.00
V3 stress_all_with_rand_reset rom_ctrl_stress_all_with_rand_reset 1.214m 5.211ms 1 1 100.00
V3 TOTAL 1 1 100.00
TOTAL 19 19 100.00