| V1 |
random |
rv_timer_random |
1.560s |
50.867us |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
rv_timer_csr_hw_reset |
1.450s |
25.629us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
rv_timer_csr_rw |
1.370s |
62.670us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
rv_timer_csr_bit_bash |
2.290s |
153.700us |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
rv_timer_csr_aliasing |
1.600s |
65.871us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
rv_timer_csr_mem_rw_with_rand_reset |
1.940s |
20.999us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
rv_timer_csr_rw |
1.370s |
62.670us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
65.871us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
random_reset |
rv_timer_random_reset |
1.690s |
236.332us |
1 |
1 |
100.00 |
| V2 |
disabled |
rv_timer_disabled |
3.630s |
2.131ms |
1 |
1 |
100.00 |
| V2 |
cfg_update_on_fly |
rv_timer_cfg_update_on_fly |
4.554m |
1.581s |
1 |
1 |
100.00 |
| V2 |
no_interrupt_test |
rv_timer_cfg_update_on_fly |
4.554m |
1.581s |
1 |
1 |
100.00 |
| V2 |
stress |
rv_timer_stress_all |
1.630s |
51.987us |
1 |
1 |
100.00 |
| V2 |
alert_test |
rv_timer_alert_test |
1.540s |
113.843us |
1 |
1 |
100.00 |
| V2 |
intr_test |
rv_timer_intr_test |
1.550s |
14.910us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
rv_timer_tl_errors |
3.210s |
1.500ms |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
rv_timer_tl_errors |
3.210s |
1.500ms |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
rv_timer_csr_hw_reset |
1.450s |
25.629us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.370s |
62.670us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
65.871us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.710s |
40.070us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
rv_timer_csr_hw_reset |
1.450s |
25.629us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_rw |
1.370s |
62.670us |
1 |
1 |
100.00 |
|
|
rv_timer_csr_aliasing |
1.600s |
65.871us |
1 |
1 |
100.00 |
|
|
rv_timer_same_csr_outstanding |
1.710s |
40.070us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
8 |
8 |
100.00 |
| V2S |
tl_intg_err |
rv_timer_sec_cm |
1.880s |
101.424us |
1 |
1 |
100.00 |
|
|
rv_timer_tl_intg_err |
2.350s |
163.394us |
1 |
1 |
100.00 |
| V2S |
sec_cm_bus_integrity |
rv_timer_tl_intg_err |
2.350s |
163.394us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
2 |
2 |
100.00 |
| V3 |
min_value |
rv_timer_min |
1.570s |
15.822us |
1 |
1 |
100.00 |
| V3 |
max_value |
rv_timer_max |
1.510s |
14.652us |
1 |
1 |
100.00 |
| V3 |
stress_all_with_rand_reset |
rv_timer_stress_all_with_rand_reset |
26.460s |
17.294ms |
1 |
1 |
100.00 |
| V3 |
|
TOTAL |
|
|
3 |
3 |
100.00 |
|
|
TOTAL |
|
|
19 |
19 |
100.00 |