SPI_DEVICE/1R1W Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	46.090s	5.305ms	1	1	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	2.010s	80.980us	1	1	100.00
V1	csr_rw	spi_device_csr_rw	2.010s	135.129us	1	1	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	15.320s	1.397ms	1	1	100.00
V1	csr_aliasing	spi_device_csr_aliasing	6.430s	671.743us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	3.450s	273.932us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.010s	135.129us	1	1	100.00
		spi_device_csr_aliasing	6.430s	671.743us	1	1	100.00
V1	mem_walk	spi_device_mem_walk	1.870s	14.435us	1	1	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.530s	24.343us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	csb_read	spi_device_csb_read	1.680s	18.681us	1	1	100.00
V2	mem_parity	spi_device_mem_parity	1.930s	1.935us	0	1	0.00
V2	mem_cfg	spi_device_ram_cfg	1.500s	3.759us	0	1	0.00
V2	tpm_read	spi_device_tpm_rw	1.840s	231.129us	1	1	100.00
V2	tpm_write	spi_device_tpm_rw	1.840s	231.129us	1	1	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	2.790s	463.372us	1	1	100.00
		spi_device_tpm_sts_read	2.080s	174.861us	1	1	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	34.020s	25.705ms	1	1	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	5.180s	922.669us	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	4.660s	369.927us	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	4.660s	369.927us	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_info_slots	spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_read_status	spi_device_intercept	8.140s	5.061ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_read_jedec	spi_device_intercept	8.140s	5.061ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_read_sfdp	spi_device_intercept	8.140s	5.061ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_fast_read	spi_device_intercept	8.140s	5.061ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	cmd_read_pipeline	spi_device_intercept	8.140s	5.061ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	flash_cmd_upload	spi_device_upload	11.740s	4.637ms	1	1	100.00
V2	mailbox_command	spi_device_mailbox	13.940s	1.602ms	1	1	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.940s	1.602ms	1	1	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.940s	1.602ms	1	1	100.00
V2	cmd_read_buffer	spi_device_flash_mode	4.630s	313.380us	1	1	100.00
		spi_device_read_buffer_direct	3.790s	503.903us	1	1	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.940s	1.602ms	1	1	100.00
		spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	quad_spi	spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	dual_spi	spi_device_flash_all	1.396m	12.186ms	1	1	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	3.880s	144.397us	1	1	100.00
V2	write_enable_disable	spi_device_cfg_cmd	3.880s	144.397us	1	1	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	46.090s	5.305ms	1	1	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	4.960m	48.592ms	1	1	100.00
V2	stress_all	spi_device_stress_all	1.924m	29.378ms	1	1	100.00
V2	alert_test	spi_device_alert_test	1.920s	45.150us	1	1	100.00
V2	intr_test	spi_device_intr_test	1.690s	52.413us	1	1	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	5.300s	307.681us	1	1	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	5.300s	307.681us	1	1	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	2.010s	80.980us	1	1	100.00
		spi_device_csr_rw	2.010s	135.129us	1	1	100.00
		spi_device_csr_aliasing	6.430s	671.743us	1	1	100.00
		spi_device_same_csr_outstanding	3.960s	91.202us	1	1	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	2.010s	80.980us	1	1	100.00
		spi_device_csr_rw	2.010s	135.129us	1	1	100.00
		spi_device_csr_aliasing	6.430s	671.743us	1	1	100.00
		spi_device_same_csr_outstanding	3.960s	91.202us	1	1	100.00
V2		TOTAL			20	22	90.91
V2S	tl_intg_err	spi_device_sec_cm	2.150s	71.203us	1	1	100.00
		spi_device_tl_intg_err	7.540s	399.302us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	7.540s	399.302us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	1.110m	22.320ms	1	1	100.00
		TOTAL			31	33	93.94

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.77775719748106029897464342375211721923574565027289182025396789431859835463530
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   1560128 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[79])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   1560128 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   1560128 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[975])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.45058658062517906656874351522055614226650341623003525991932213864892598095279
      Line 71, in log /nightly/runs/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @   1461547 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcb5124 [110010110101000100100100] vs 0x0 [0])
        UVM_ERROR @   1547547 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x46469b [10001100100011010011011] vs 0x0 [0])
        UVM_ERROR @   1568547 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5afc1d [10110101111110000011101] vs 0x0 [0])
        UVM_ERROR @   1662547 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc8eff3 [110010001110111111110011] vs 0x0 [0])
        UVM_ERROR @   1678547 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xc926d7 [110010010010011011010111] vs 0x0 [0])