SPI_HOST Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	19.000s	1.767ms	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	4.000s	18.185us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	3.000s	21.441us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	5.000s	232.109us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	4.000s	19.484us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	4.000s	152.032us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	3.000s	21.441us	1	1	100.00
		spi_host_csr_aliasing	4.000s	19.484us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	4.000s	15.506us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	3.000s	62.895us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	4.000s	26.268us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	6.000s	62.146us	1	1	100.00
		spi_host_error_cmd	5.000s	20.952us	1	1	100.00
		spi_host_event	21.000s	2.394ms	1	1	100.00
V2	clock_rate	spi_host_speed	6.000s	309.445us	1	1	100.00
V2	speed	spi_host_speed	6.000s	309.445us	1	1	100.00
V2	chip_select_timing	spi_host_speed	6.000s	309.445us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	6.000s	102.192us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	4.000s	36.338us	1	1	100.00
V2	cpol_cpha	spi_host_speed	6.000s	309.445us	1	1	100.00
V2	full_cycle	spi_host_speed	6.000s	309.445us	1	1	100.00
V2	duplex	spi_host_smoke	19.000s	1.767ms	1	1	100.00
V2	tx_rx_only	spi_host_smoke	19.000s	1.767ms	1	1	100.00
V2	stress_all	spi_host_stress_all	22.000s	865.150us	1	1	100.00
V2	spien	spi_host_spien	8.000s	631.882us	1	1	100.00
V2	stall	spi_host_status_stall	18.000s	1.235ms	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	11.000s	2.084ms	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	6.000s	62.146us	1	1	100.00
V2	alert_test	spi_host_alert_test	3.000s	16.870us	1	1	100.00
V2	intr_test	spi_host_intr_test	4.000s	30.917us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	4.000s	55.477us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	4.000s	55.477us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	4.000s	18.185us	1	1	100.00
		spi_host_csr_rw	3.000s	21.441us	1	1	100.00
		spi_host_csr_aliasing	4.000s	19.484us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.236us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	4.000s	18.185us	1	1	100.00
		spi_host_csr_rw	3.000s	21.441us	1	1	100.00
		spi_host_csr_aliasing	4.000s	19.484us	1	1	100.00
		spi_host_same_csr_outstanding	4.000s	22.236us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	spi_host_tl_intg_err	4.000s	56.068us	1	1	100.00
		spi_host_sec_cm	4.000s	133.651us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	4.000s	56.068us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	1.383m	4.627ms	1	1	100.00
		TOTAL			26	26	100.00