SRAM_CTRL/RET Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	9.290s	1.339ms	1	1	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	1.620s	57.202us	1	1	100.00
V1	csr_rw	sram_ctrl_csr_rw	1.500s	13.582us	1	1	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	2.870s	298.992us	1	1	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.620s	25.624us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	1.780s	153.334us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	1.500s	13.582us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	25.624us	1	1	100.00
V1	mem_walk	sram_ctrl_mem_walk	8.870s	694.412us	1	1	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	3.190s	361.090us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	multiple_keys	sram_ctrl_multiple_keys	8.150m	40.853ms	1	1	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	2.928m	5.072ms	1	1	100.00
V2	bijection	sram_ctrl_bijection	31.170s	5.433ms	1	1	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	7.615m	16.428ms	1	1	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	5.440s	2.330ms	1	1	100.00
V2	executable	sram_ctrl_executable	5.874m	9.556ms	1	1	100.00
V2	partial_access	sram_ctrl_partial_access	15.420s	1.201ms	1	1	100.00
		sram_ctrl_partial_access_b2b	6.845m	21.313ms	1	1	100.00
V2	max_throughput	sram_ctrl_max_throughput	25.980s	420.257us	1	1	100.00
		sram_ctrl_throughput_w_partial_write	8.590s	76.510us	1	1	100.00
		sram_ctrl_throughput_w_readback	55.250s	286.194us	1	1	100.00
V2	regwen	sram_ctrl_regwen	11.380s	486.195us	1	1	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	1.690s	37.233us	1	1	100.00
V2	stress_all	sram_ctrl_stress_all	18.555m	88.864ms	1	1	100.00
V2	alert_test	sram_ctrl_alert_test	1.480s	12.510us	1	1	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	2.690s	33.748us	1	1	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	2.690s	33.748us	1	1	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	1.620s	57.202us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	13.582us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	25.624us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	14.525us	1	1	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	1.620s	57.202us	1	1	100.00
		sram_ctrl_csr_rw	1.500s	13.582us	1	1	100.00
		sram_ctrl_csr_aliasing	1.620s	25.624us	1	1	100.00
		sram_ctrl_same_csr_outstanding	1.550s	14.525us	1	1	100.00
V2		TOTAL			17	17	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	3.620s	2.959ms	1	1	100.00
V2S	tl_intg_err	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
		sram_ctrl_tl_intg_err	3.690s	763.547us	1	1	100.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	3.690s	763.547us	1	1	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	11.380s	486.195us	1	1	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	11.380s	486.195us	1	1	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	1.500s	13.582us	1	1	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	5.874m	9.556ms	1	1	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	5.874m	9.556ms	1	1	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	5.874m	9.556ms	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	5.440s	2.330ms	1	1	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	1.950s	43.382us	1	1	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	3.620s	2.959ms	1	1	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	1.900s	30.334us	0	1	0.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	9.290s	1.339ms	1	1	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	9.290s	1.339ms	1	1	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	5.874m	9.556ms	1	1	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	5.440s	2.330ms	1	1	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	9.290s	1.339ms	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.410s	4.905us	0	1	0.00
V2S		TOTAL			3	5	60.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	7.020s	1.014ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			29	31	93.55

Failure Buckets

• UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test sram_ctrl_readback_err has 1 failures.

    • 0.sram_ctrl_readback_err.81545048989794564973074487896342501546402511917186001482820138570818521061234
      Line 93, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_readback_err/latest/run.log

        UVM_ERROR @  30333864 ps: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x36) != exp (0x3c)
        UVM_INFO @  30333864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.9147751183254137214867607684516050137259098150946189850404440365854673333319
      Line 94, in log /nightly/runs/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   4905008 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   4905008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---