UART Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: df6b01c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	2.340s	646.632us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	1.590s	51.699us	1	1	100.00
V1	csr_rw	uart_csr_rw	1.880s	18.246us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	2.730s	76.895us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	1.730s	106.598us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	1.600s	14.569us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	1.880s	18.246us	1	1	100.00
		uart_csr_aliasing	1.730s	106.598us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	1.017m	118.376ms	1	1	100.00
V2	parity	uart_smoke	2.340s	646.632us	1	1	100.00
		uart_tx_rx	1.017m	118.376ms	1	1	100.00
V2	parity_error	uart_intr	15.560s	55.225ms	1	1	100.00
		uart_rx_parity_err	28.570s	431.933ms	1	1	100.00
V2	watermark	uart_tx_rx	1.017m	118.376ms	1	1	100.00
		uart_intr	15.560s	55.225ms	1	1	100.00
V2	fifo_full	uart_fifo_full	42.490s	35.048ms	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	1.243m	302.984ms	1	1	100.00
V2	fifo_reset	uart_fifo_reset	26.350s	22.055ms	1	1	100.00
V2	rx_frame_err	uart_intr	15.560s	55.225ms	1	1	100.00
V2	rx_break_err	uart_intr	15.560s	55.225ms	1	1	100.00
V2	rx_timeout	uart_intr	15.560s	55.225ms	1	1	100.00
V2	perf	uart_perf	1.139m	21.873ms	1	1	100.00
V2	sys_loopback	uart_loopback	5.890s	11.882ms	1	1	100.00
V2	line_loopback	uart_loopback	5.890s	11.882ms	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	11.960s	42.023ms	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	2.470s	4.794ms	1	1	100.00
V2	tx_overide	uart_tx_ovrd	6.420s	7.381ms	1	1	100.00
V2	rx_oversample	uart_rx_oversample	7.560s	2.019ms	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	2.686m	116.301ms	1	1	100.00
V2	stress_all	uart_stress_all	10.937m	196.886ms	1	1	100.00
V2	alert_test	uart_alert_test	1.540s	38.499us	1	1	100.00
V2	intr_test	uart_intr_test	1.550s	117.234us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	2.160s	70.330us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	2.160s	70.330us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	1.590s	51.699us	1	1	100.00
		uart_csr_rw	1.880s	18.246us	1	1	100.00
		uart_csr_aliasing	1.730s	106.598us	1	1	100.00
		uart_same_csr_outstanding	1.680s	15.837us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	1.590s	51.699us	1	1	100.00
		uart_csr_rw	1.880s	18.246us	1	1	100.00
		uart_csr_aliasing	1.730s	106.598us	1	1	100.00
		uart_same_csr_outstanding	1.680s	15.837us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	1.910s	39.605us	1	1	100.00
		uart_tl_intg_err	1.790s	209.430us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.790s	209.430us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	15.430s	1.978ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			25	27	92.59

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * has 1 failures:

  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.8578153630598905288393658374272728453161371834950529422758018988250235748098
      Line 73, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @ 38251948977 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
        UVM_ERROR @ 38251948977 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 38251948977 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 38344768087 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 39111775757 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 6,                                 clk_pulses: 0
      

• UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * has 1 failures:

  • Test uart_stress_all_with_rand_reset has 1 failures.

    • 0.uart_stress_all_with_rand_reset.42586111109009212473138692450760405704668791328860462072922889801582479216540
      Line 111, in log /nightly/runs/scratch/master/uart-sim-vcs/0.uart_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1723711430 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 5,                                 clk_pulses: 0
        UVM_ERROR @ 1723721847 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
        UVM_ERROR @ 1723732264 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
        UVM_INFO @ 1738170226 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/296
        UVM_INFO @ 1784817552 ps: (cip_base_vseq__tl_errors.svh:290) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 7/296