CHIP Simulation Results

Tuesday June 10 2025 17:06:39 UTC

GitHub Revision: `df6b01c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	23.815s		0	1	0.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	23.815s		0	1	0.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	6.079m		0	1	0.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	6.591m		0	1	0.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	6.071m		0	1	0.00
V1	chip_sw_gpio_out	chip_sw_gpio	5.708m	6.593ms	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	5.708m	6.593ms	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	5.708m	6.593ms	1	1	100.00
V1	chip_sw_example_tests	chip_sw_example_rom	25.910s	10.220us	0	1	0.00
		chip_sw_example_manufacturer	33.180s		0	1	0.00
		chip_sw_example_concurrency	4.268m	4.433ms	1	1	100.00
		chip_sw_uart_smoketest_signed	22.060s		0	1	0.00
V1	csr_bit_bash	chip_csr_bit_bash	8.120s		0	1	0.00
V1	csr_aliasing	chip_csr_aliasing	7.880s		0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	7.880s		0	1	0.00
V1	xbar_smoke	xbar_smoke	18.920s	57.969us	1	1	100.00
V1		TOTAL			3	12	25.00
V2	chip_sw_spi_device_flash_mode	chip_sw_uart_tx_rx_bootstrap	6.808m		0	1	0.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	11.342m	7.981ms	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	4.296m	5.775ms	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.147m		0	1	0.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.997m		0	1	0.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	5.955m		0	1	0.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	6.059m		0	1	0.00
V2	chip_pin_mux	chip_padctrl_attributes	4.940s		0	1	0.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.940s		0	1	0.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	27.584s		0	1	0.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	26.145s		0	1	0.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	6.414m		0	1	0.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	6.414m		0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	3.215m	4.082ms	0	1	0.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	2.941m	3.788ms	0	1	0.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	6.486m	15.720ms	0	1	0.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.080s		0	1	0.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	11.901s		0	1	0.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.033m	11.539ms	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.163m	6.681ms	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	21.715m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	21.715m	18.017ms	0	1	0.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	1.298m		0	1	0.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.342m	5.131ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	5.342m	5.131ms	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	5.189m	18.025ms	0	1	0.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.386m	5.391ms	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	4.940m	4.368ms	1	1	100.00
		chip_sw_aes_idle	4.363m	4.287ms	1	1	100.00
		chip_sw_hmac_enc_idle	4.825m	3.891ms	1	1	100.00
		chip_sw_kmac_idle	3.657m	5.857ms	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.638m	12.023ms	0	1	0.00
		chip_sw_clkmgr_off_hmac_trans	12.332m	12.015ms	0	1	0.00
		chip_sw_clkmgr_off_kmac_trans	11.371m	12.021ms	0	1	0.00
		chip_sw_clkmgr_off_otbn_trans	13.502m	11.738ms	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_lc	11.784s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.735s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.132s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.091s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.287s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	11.784s		0	1	0.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.735s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.132s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.091s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.287s		0	1	0.00
V2	chip_sw_clkmgr_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	24.112s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.770s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	33.070s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.070s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.530s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.184s		0	1	0.00
		chip_sw_clkmgr_jitter	2.983m	3.736ms	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	3.998m	4.494ms	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	16.197s		0	1	0.00
		chip_sw_aes_enc_jitter_en_reduced_freq	38.300s	10.120us	0	1	0.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	35.580s	10.320us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en_reduced_freq	33.030s	10.280us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	36.220s	10.140us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	37.620s	10.200us	0	1	0.00
		chip_sw_csrng_edn_concurrency_reduced_freq	12.436s		0	1	0.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	12.010s		0	1	0.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.548s		0	1	0.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	12.446s		0	1	0.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	8.159m	12.755ms	1	1	100.00
V2	chip_sw_pwrmgr_sleep_all_reset_reqs	chip_sw_aon_timer_wdog_bite_reset	5.342m	5.131ms	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	1.307m		0	1	0.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	8.159m	12.755ms	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	14.799s		0	1	0.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	25.214s		0	1	0.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	1.672m		0	1	0.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	19.864s		0	1	0.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	36.197s		0	1	0.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	6.486m	15.720ms	0	1	0.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	20.444m	20.015ms	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	7.008m	8.990ms	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	7.572m	9.610ms	0	1	0.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.261m	5.391ms	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	28.194s		0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.895s		0	1	0.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	11.862s		0	1	0.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	7.572m	9.610ms	0	1	0.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	15.289s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	11.068s		0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	11.357s		0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	11.226s		0	1	0.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	11.145s		0	1	0.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	19.294s		0	1	0.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.895s		0	1	0.00
V2	chip_sw_lc_ctrl_jtag_access	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_lc_ctrl_otp_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.407m		0	1	0.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_dpe_key_derivation_prod	6.285m	5.187ms	0	1	0.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.615m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	4.498m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	4.271m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	4.262m		0	1	0.00
		chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
		chip_sw_keymgr_dpe_key_derivation	6.654m	6.188ms	0	1	0.00
		chip_sw_rom_ctrl_integrity_check	7.739m	12.672ms	1	1	100.00
		chip_sw_sram_ctrl_execution_main	17.172s		0	1	0.00
		chip_prim_tl_access	2.574m	4.240ms	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	11.784s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.735s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.132s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.792s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.091s		0	1	0.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.287s		0	1	0.00
		chip_rv_dm_lc_disabled	6.033m	11.539ms	1	1	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.636m	4.694ms	1	1	100.00
		chip_sw_aes_enc_jitter_en	37.770s	10.160us	0	1	0.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	3.392m	3.514ms	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.363m	4.287ms	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.494m	4.145ms	1	1	100.00
		chip_sw_hmac_enc_jitter_en	33.070s	10.200us	0	1	0.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.825m	3.891ms	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	3.116m	4.440ms	1	1	100.00
		chip_sw_kmac_mode_kmac	4.841m	3.703ms	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	34.530s	10.340us	0	1	0.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_dpe_key_derivation	6.654m	6.188ms	0	1	0.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	30.370s	10.400us	0	1	0.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.498m	4.084ms	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.657m	5.857ms	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	12.496s		0	1	0.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	12.496s		0	1	0.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.171s		0	1	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.296m	5.466ms	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	13.159s		0	1	0.00
V2	chip_sw_keymgr_dpe_key_derivation	chip_sw_keymgr_dpe_key_derivation	6.654m	6.188ms	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.070s	10.400us	0	1	0.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	1.191m		0	1	0.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	24.112s		0	1	0.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	4.940m	4.368ms	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	4.940m	4.368ms	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	4.940m	4.368ms	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	8.076m	5.825ms	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	7.739m	12.672ms	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	7.739m	12.672ms	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	7.850m	7.522ms	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.184s		0	1	0.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	17.172s		0	1	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
		chip_sw_data_integrity_escalation	6.414m		0	1	0.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_otp_ctrl_keys	chip_sw_otbn_mem_scramble	8.076m	5.825ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.654m	6.188ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.850m	7.522ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.983m	4.688ms	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_otbn_mem_scramble	8.076m	5.825ms	1	1	100.00
		chip_sw_keymgr_dpe_key_derivation	6.654m	6.188ms	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access	7.850m	7.522ms	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	2.983m	4.688ms	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	11.029s		0	1	0.00
V2	chip_sw_otp_ctrl_hw_cfg	chip_sw_lc_ctrl_otp_hw_cfg	5.407m		0	1	0.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	4.615m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_dev	4.498m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_prod	4.271m		0	1	0.00
		chip_sw_otp_ctrl_lc_signals_rma	4.262m		0	1	0.00
		chip_sw_lc_ctrl_transition	3.239m		0	1	0.00
		chip_prim_tl_access	2.574m	4.240ms	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	2.574m	4.240ms	1	1	100.00
V2	chip_sw_otp_ctrl_nvm_cnt	chip_sw_otp_ctrl_nvm_cnt	4.043m		0	1	0.00
V2	chip_sw_otp_ctrl_sw_parts	chip_sw_otp_ctrl_sw_parts	3.462m		0	1	0.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	12.010s		0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_otbn_ecdsa_op_irq_jitter_en	24.112s		0	1	0.00
		chip_sw_aes_enc_jitter_en	37.770s	10.160us	0	1	0.00
		chip_sw_hmac_enc_jitter_en	33.070s	10.200us	0	1	0.00
		chip_sw_keymgr_dpe_key_derivation_jitter_en	42.070s	10.400us	0	1	0.00
		chip_sw_kmac_mode_kmac_jitter_en	34.530s	10.340us	0	1	0.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	15.184s		0	1	0.00
		chip_sw_clkmgr_jitter	2.983m	3.736ms	1	1	100.00
V2	chip_sw_soc_proxy_external_reset_requests	chip_sw_soc_proxy_smoketest	5.955m	6.339ms	1	1	100.00
V2	chip_sw_soc_proxy_external_irqs	chip_sw_soc_proxy_smoketest	5.955m	6.339ms	1	1	100.00
V2	chip_sw_soc_proxy_external_alerts	chip_sw_soc_proxy_external_alerts	5.253m	5.424ms	0	1	0.00
V2	chip_sw_soc_proxy_external_wakeup_requests	chip_sw_soc_proxy_external_wakeup	3.645m	4.602ms	0	1	0.00
V2	chip_sw_soc_proxy_gpios	chip_sw_soc_proxy_gpios	2.882m	3.739ms	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	7.284m	6.069ms	0	1	0.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	5.160m	5.143ms	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	3.749m	4.430ms	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	2.983m	4.688ms	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	20.444m	20.015ms	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	20.444m	20.015ms	0	1	0.00
V2	chip_sw_smoketest	chip_sw_aes_smoketest	3.873m	4.848ms	1	1	100.00
		chip_sw_aon_timer_smoketest	3.667m	4.092ms	1	1	100.00
		chip_sw_clkmgr_smoketest	3.104m	3.773ms	1	1	100.00
		chip_sw_csrng_smoketest	3.141m	4.029ms	1	1	100.00
		chip_sw_gpio_smoketest	3.951m	5.600ms	1	1	100.00
		chip_sw_hmac_smoketest	4.356m	5.475ms	1	1	100.00
		chip_sw_kmac_smoketest	3.943m	4.604ms	1	1	100.00
		chip_sw_otbn_smoketest	5.090m	5.352ms	1	1	100.00
		chip_sw_otp_ctrl_smoketest	3.687m	5.153ms	1	1	100.00
		chip_sw_rv_plic_smoketest	2.972m	4.201ms	1	1	100.00
		chip_sw_rv_timer_smoketest	4.519m	5.398ms	1	1	100.00
		chip_sw_rstmgr_smoketest	3.330m	5.256ms	1	1	100.00
		chip_sw_sram_ctrl_smoketest	3.203m	4.196ms	1	1	100.00
		chip_sw_uart_smoketest	3.151m	4.914ms	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	35.509s		0	1	0.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	22.060s		0	1	0.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	6.808m		0	1	0.00
V2	chip_sw_secure_boot	base_rom_e2e_smoke	11.633s		0	1	0.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.990m	5.494ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	3.309m	6.223ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	3.215m	5.528ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.670m	5.826ms	1	1	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	2.029m		0	1	0.00
		chip_rv_dm_lc_disabled	6.033m	11.539ms	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	54.949s		0	1	0.00
		chip_sw_lc_walkthrough_prod	37.727s		0	1	0.00
		chip_sw_lc_walkthrough_prodend	18.978s		0	1	0.00
		chip_sw_lc_walkthrough_rma	22.025s		0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	2.029m		0	1	0.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.052m		0	1	0.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.020m		0	1	0.00
		rom_volatile_raw_unlock	10.914s		0	1	0.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	11.023s		0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	14.652s		0	1	0.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	15.278s		0	1	0.00
V2	tl_d_oob_addr_access	chip_tl_errors	2.845m	3.944ms	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	2.845m	3.944ms	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	7.880s		0	1	0.00
		chip_same_csr_outstanding	8.090s		0	1	0.00
V2	tl_d_partial_access	chip_csr_aliasing	7.880s		0	1	0.00
		chip_same_csr_outstanding	8.090s		0	1	0.00
V2	xbar_base_random_sequence	xbar_random	15.460s	31.762us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	8.700s	11.217us	1	1	100.00
		xbar_smoke_large_delays	4.902m	2.760ms	1	1	100.00
		xbar_smoke_slow_rsp	5.479m	2.260ms	1	1	100.00
		xbar_random_zero_delays	1.273m	68.674us	1	1	100.00
		xbar_random_large_delays	16.111m	8.775ms	1	1	100.00
		xbar_random_slow_rsp	16.249m	6.279ms	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	52.810s	35.969us	1	1	100.00
		xbar_error_and_unmapped_addr	9.670s	17.254us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	2.159m	391.736us	1	1	100.00
		xbar_error_and_unmapped_addr	9.670s	17.254us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	3.892m	763.774us	1	1	100.00
		xbar_access_same_device_slow_rsp	24.808m	9.569ms	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.118m	69.048us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	6.514m	433.918us	1	1	100.00
		xbar_stress_all_with_error	3.391m	717.909us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	4.022m	79.449us	1	1	100.00
		xbar_stress_all_with_reset_error	10.284m	503.053us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	12.136s		0	1	0.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	11.085s		0	1	0.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	11.479s		0	1	0.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	14.483s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	10.419s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	10.547s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	10.979s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	10.581s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	10.887s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	11.975s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.136s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	11.356s		0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	10.820s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	11.476s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	11.879s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	11.550s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.955s		0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	13.620s		0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	12.660s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	12.949s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	12.449s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	13.042s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	13.503s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	13.813s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	11.428s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	13.341s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	12.124s		0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	12.694s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	12.316s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	12.320s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	12.369s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	11.970s		0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	12.414s		0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	12.083s		0	1	0.00
		rom_e2e_asm_init_dev	11.699s		0	1	0.00
		rom_e2e_asm_init_prod	11.235s		0	1	0.00
		rom_e2e_asm_init_prod_end	11.591s		0	1	0.00
		rom_e2e_asm_init_rma	10.952s		0	1	0.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	11.342s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas	11.751s		0	1	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	10.580s		0	1	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	10.818s		0	1	0.00
V2		TOTAL			65	205	31.71
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.082m	5.345ms	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	3.063m	3.594ms	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	11.128s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.487s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.874s		0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	13.016s		0	1	0.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.416m	12.010ms	0	1	0.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.747m		0	1	0.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	14.796m	14.055ms	1	1	100.00
V3	chip_sw_coremark	chip_sw_coremark	13.762s		0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.507s		0	1	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	11.128s		0	1	0.00
		rom_e2e_jtag_debug_dev	11.487s		0	1	0.00
		rom_e2e_jtag_debug_rma	12.874s		0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	10.756s		0	1	0.00
		rom_e2e_jtag_inject_dev	10.910s		0	1	0.00
		rom_e2e_jtag_inject_rma	11.370s		0	1	0.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	1.058m		0	1	0.00
V3		TOTAL			1	12	8.33
	Unmapped tests	chip_sw_rstmgr_rst_cnsty_escalation	19.291m	15.460ms	1	1	100.00
		chip_plic_all_irqs_0	8.709m	6.141ms	1	1	100.00
		chip_plic_all_irqs_10	9.153m	7.109ms	1	1	100.00
		chip_sw_dma_inline_hashing	4.542m	4.230ms	1	1	100.00
		chip_sw_dma_abort	4.540m	5.752ms	0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_otbn	11.540s		0	1	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw	11.575s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn	11.049s		0	1	0.00
		rom_e2e_sigverify_mod_exp_dev_sw	12.752s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn	11.689s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_sw	10.960s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn	10.942s		0	1	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw	11.682s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn	11.202s		0	1	0.00
		rom_e2e_sigverify_mod_exp_rma_sw	11.796s		0	1	0.00
		chip_sw_mbx_smoketest	4.135m	5.706ms	1	1	100.00
		TOTAL			76	247	30.77

Failure Buckets

Job returned non-zero exit code has 136 failures:

Test chip_sw_example_manufacturer has 1 failures.

0.chip_sw_example_manufacturer.45502438720046806098817933487186248038717159005725848201247659710237657547362
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_manufacturer/latest/run.log

  Analyzing: target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (1 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '@@+hooks+manufacturer_test_hooks//:example_test_sim_dv' failed; build aborted: Target @@+hooks+manufacturer_test_hooks//:example_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      @@+hooks+manufacturer_test_hooks//:example_test_sim_dv (b2ea6a)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 16.002s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_data_integrity_escalation has 1 failures.

0.chip_sw_data_integrity_escalation.66733093883257402078771637685816599628765829485157430160542447642508415196684
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_data_integrity_escalation/latest/run.log

  Analyzing: target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv' failed; build aborted: Target //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests/sim_dv:data_integrity_escalation_reset_test_sim_dv (9b5fc3)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 367.279s, Critical Path: 0.01s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_wake has 1 failures.

0.chip_sw_sleep_pin_wake.49713451637970634217282966041841670128029727773197369721177471124105504150628
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_wake/latest/run.log

  Analyzing: target //sw/device/tests:sleep_pin_wake_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_wake_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_wake_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_wake_test_sim_dv (b37110)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 7.607s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_sleep_pin_retention has 1 failures.

0.chip_sw_sleep_pin_retention.70632314103711305540515659713102862802281022856372593634500348674467600070439
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_sleep_pin_retention/latest/run.log

  Target //sw/device/tests:sleep_pin_retention_test_sim_dv failed to build
  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:sleep_pin_retention_test_sim_dv' failed; build aborted: Target //sw/device/tests:sleep_pin_retention_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:sleep_pin_retention_test_sim_dv (dbe87c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 15.366s, Critical Path: 0.05s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test chip_sw_uart_tx_rx has 1 failures.

0.chip_sw_uart_tx_rx.42710587651735090123128033167204195914445851011582825485929577850113744408097
Log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_uart_tx_rx/latest/run.log

  Analyzing: target //sw/device/tests:uart_tx_rx_test_sim_dv (0 packages loaded, 0 targets configured)

  Use --verbose_failures to see the command lines of failed build steps.
  ERROR: Analysis of target '//sw/device/tests:uart_tx_rx_test_sim_dv' failed; build aborted: Target //sw/device/tests:uart_tx_rx_test_sim_dv is incompatible and cannot be built, but was explicitly requested.
  Dependency chain:
      //sw/device/tests:uart_tx_rx_test_sim_dv (0ab48c)   <-- target platform (//toolchain:opentitan_platform) didn't satisfy constraint @@platforms//:incompatible
  INFO: Elapsed time: 13.609s, Critical Path: 0.02s
  INFO: 1 process: 1 internal.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/runs/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 131 more tests.

UVM_FATAL @ * us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_*] Check failed (ret) Failed to read line from "kJitterEnabled.dat" has 9 failures:
- Test chip_sw_aes_enc_jitter_en has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en.335586671770357037357141110876730437215156116022349650661728975609348155721
    Line 448, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.160001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_hmac_enc_jitter_en has 1 failures.
  - 0.chip_sw_hmac_enc_jitter_en.49980082335570228773051843320800364313986035810825869724717863855557004998380
    Line 408, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_hmac_enc_jitter_en/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_keymgr_dpe_key_derivation_jitter_en has 1 failures.
  - 0.chip_sw_keymgr_dpe_key_derivation_jitter_en.12467429076991246348338725504389427161825123403449402944138277829600617577921
    Line 406, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_jitter_en/latest/run.log
```
  UVM_FATAL @  10.400001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_kmac_mode_kmac_jitter_en has 1 failures.
  - 0.chip_sw_kmac_mode_kmac_jitter_en.102443650909440497959233605613952262226875488551974297766616378569488297620687
    Line 421, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_mode_kmac_jitter_en/latest/run.log
```
  UVM_FATAL @  10.340001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aes_enc_jitter_en_reduced_freq has 1 failures.
  - 0.chip_sw_aes_enc_jitter_en_reduced_freq.26201855793124791810289286898183000334615449710051175072201383824174800236411
    Line 443, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest/run.log
```
  UVM_FATAL @  10.120001 us: (dv_utils_pkg.sv:266) [dv_utils_pkg::sw_symbol_get_addr_size.unnamed$$_1] Check failed (ret) Failed to read line from "kJitterEnabled.dat"
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 4 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode has 3 failures:
- Test chip_csr_bit_bash has 1 failures.
  - 0.chip_csr_bit_bash.11784708770158669751821848127952121260609819617861847744298916078693799140495
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_bit_bash/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.28994853764322910111019811668048121046299975971285423855702656764510716065298
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_same_csr_outstanding has 1 failures.
  - 0.chip_same_csr_outstanding.24337669083835270708785109418703038757288807128673035101156596288339526303311
    Line 131, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @   0.000000 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Otp]] file otp_ctrl_img_rma.vmem could not be opened for r mode
  UVM_INFO @   0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.1085240799086103167014928054684221505566280454766302951488791540218418781913
Line 534, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 20015.424613 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 20000000 ns

  UVM_INFO @ 20015.424613 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_irq has 1 failures.

0.chip_sw_aon_timer_irq.32787466825511176924246039889408794236496090522935701869765078049457979676773
Line 571, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_irq/latest/run.log

  UVM_ERROR @ 18016.834572 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18016.834572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_aon_timer_sleep_wdog_sleep_pause has 1 failures.

0.chip_sw_aon_timer_sleep_wdog_sleep_pause.12070543889163197849933507251696887295227519218188969861026778837627792511290
Line 539, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest/run.log

  UVM_ERROR @ 18024.520945 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 18024.520945 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

Test chip_sw_clkmgr_off_aes_trans has 1 failures.

0.chip_sw_clkmgr_off_aes_trans.43471180186338431633746184359927309957043297861643523244743214296622298727730
Line 433, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_aes_trans/latest/run.log

  UVM_ERROR @ 12022.898630 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12022.898630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_hmac_trans has 1 failures.

0.chip_sw_clkmgr_off_hmac_trans.101069459662480921062032970304711406460351342278672426924636007524270764108760
Line 436, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_hmac_trans/latest/run.log

  UVM_ERROR @ 12014.511383 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12014.511383 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_clkmgr_off_kmac_trans has 1 failures.

0.chip_sw_clkmgr_off_kmac_trans.89726307987755618706098949769491376822706555147769836587124454051933026592842
Line 439, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_clkmgr_off_kmac_trans/latest/run.log

  UVM_ERROR @ 12021.053105 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns

  UVM_INFO @ 12021.053105 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (* [*] vs * [*]) has 2 failures:

Test chip_sw_keymgr_dpe_key_derivation has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation.88823051937680789332611901263938322835441405860893968463699091963185492827356
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation/latest/run.log

  UVM_ERROR @ 6188.479282 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (37431463062981645427157275928847826484856348270295339103853967541984180806790 [0x52c175123972a2aaab3b5bc9afd5c58e89cc850d83c9f87689bf588b4df3a486] vs 106367917735133652863774994584670214843507064055983128286300903733822702189836 [0xeb2a1ba2fd5de52accd36e4e22c903ac08f86f568438be14e07ce769999b7d0c])
  UVM_INFO @ 6188.479282 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_keymgr_dpe_key_derivation_prod has 1 failures.

0.chip_sw_keymgr_dpe_key_derivation_prod.97413578955919089391884438282352937997634953365389025215042907092102211788116
Line 460, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_keymgr_dpe_key_derivation_prod/latest/run.log

  UVM_ERROR @ 5187.323672 us: (chip_sw_keymgr_dpe_key_derivation_vseq.sv:489) [uvm_test_top.env.virtual_sequencer.chip_sw_keymgr_dpe_key_derivation_vseq] Check failed keymgr_pkg::KeyWidth'(get_kmac_digest(kmac_key, data_arr)) == act_digest (95404286977798052978623180786191648966821773038417339183067815723326021907847 [0xd2ece9b099973d6808323296915956d20740f0f84611e4d91db48eab99153587] vs 90196359364891383613533582312745298198117146614570839993353143950971879159305 [0xc769548d4238ee749761b1bb8785f9b10b65dedde1a1a1dcff1db8248271f609])
  UVM_INFO @ 5187.323672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 2 failures:

Test chip_jtag_csr_rw has 1 failures.

0.chip_jtag_csr_rw.45533659709004959104733673913965045790529917945041283865121055561843354064296
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_csr_rw/latest/run.log

  UVM_ERROR @ 4081.540305 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'h68ed56f4  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h3  a_opcode: 'h0  a_user: 'h26964  d_param: 'h0  d_source: 'h3  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4081.540305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_jtag_mem_access has 1 failures.

0.chip_jtag_mem_access.86256324636594650932166759815453591148127413887192743040972228809926856081640
Line 6143, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_jtag_mem_access/latest/run.log

  UVM_ERROR @ 3787.825410 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@46335) { a_addr: 'h30480000  a_data: 'hfd6cba9c  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h33  a_opcode: 'h1  a_user: 'h248cc  d_param: 'h0  d_source: 'h33  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h0  d_sink: 'h0  d_user: 'h1caa  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 1, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 3787.825410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.*.scr.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_example_rom has 1 failures.
  - 0.chip_sw_example_rom.96403398010538068343686426517184292566813981466042852342151769098463451944248
    Line 417, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_example_rom/latest/run.log
```
  UVM_FATAL @  10.220001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[Rom0]] file example_test_from_rom_rom_prog_sim_dv.39.scr.vmem could not be opened for r mode
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:434) virtual_sequencer [chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 0.chip_sw_all_escalation_resets.73694059464239720282049205809316418837561780923667186733489400399254790806430
    Line 496, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 12010.340001 us: (chip_sw_base_vseq.sv:434) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_all_escalation_resets_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns

  UVM_INFO @ 12010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.15946506867587281615262222931006081375923483049741548811184084510108697575751
    Line 626, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 5774.687540 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:379)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 5774.687540 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[*] mismatch exp:* obs:* has 1 failures:
- Test chip_sw_rstmgr_alert_info has 1 failures.
  - 0.chip_sw_rstmgr_alert_info.11538770145253137896826910534280113419929551855699359027358400188559022755869
    Line 756, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rstmgr_alert_info/latest/run.log
```
  UVM_ERROR @ 9610.367736 us: (sw_logger_if.sv:526) [rstmgr_alert_info_test_sim_dv(sw/device/tests/rstmgr_alert_info_test.c:664)] CHECK-fail: alert_info.class_accum_cnt[0] mismatch exp:0x3  obs:0x1
  UVM_INFO @ 9610.367736 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (* [*] vs * [*]) Alert response incorrect! has 1 failures:
- Test chip_sw_soc_proxy_external_alerts has 1 failures.
  - 0.chip_sw_soc_proxy_external_alerts.24681010566141968785582042863936972486914213469537869713208196978933055138867
    Line 583, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_alerts/latest/run.log
```
  UVM_ERROR @ 5423.805488 us: (chip_sw_soc_proxy_external_alerts_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.chip_sw_soc_proxy_external_alerts_vseq] Check failed alert_rsp == alert_req (93824992236885 [0x555555555555] vs 93824992236886 [0x555555555556]) Alert response incorrect!
  UVM_INFO @ 5423.805488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns * has 1 failures:
- Test chip_sw_soc_proxy_external_wakeup has 1 failures.
  - 0.chip_sw_soc_proxy_external_wakeup.75662072982056227096219147380999576505111016047917294071946198331376924624009
    Line 516, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_soc_proxy_external_wakeup/latest/run.log
```
  UVM_ERROR @ 4602.050814 us: (sw_logger_if.sv:526) [soc_proxy_external_wakeup_sim_dv(sw/device/tests/soc_proxy_external_wakeup.c:50)] DIF-fail: dif_pwrmgr_get_request_sources(&pwrmgr, kDifPwrmgrReqTypeWakeup, &wakeup_req_srcs) returns 3
  UVM_INFO @ 4602.050814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after * microseconds has 1 failures:
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.22897509224504477643599594033637680448874835421864833876081605140104177496219
    Line 542, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
  UVM_ERROR @ 5131.075770 us: (sw_logger_if.sv:526) [aon_timer_wdog_bite_reset_test_sim_dv(sw/device/tests/aon_timer_wdog_bite_reset_test.c:84)] CHECK-fail: Wdog bark irq did not rise after 201 microseconds
  UVM_INFO @ 5131.075770 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for nmi_fired has 1 failures:
- Test chip_sw_rv_core_ibex_nmi_irq has 1 failures.
  - 0.chip_sw_rv_core_ibex_nmi_irq.112859620402871052205316048390945656428777940868103218167054916008014113441857
    Line 513, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_rv_core_ibex_nmi_irq/latest/run.log
```
  UVM_ERROR @ 6069.499996 us: (sw_logger_if.sv:526) [rv_core_ibex_nmi_irq_test_sim_dv(sw/device/tests/rv_core_ibex_nmi_irq_test.c:172)] CHECK-fail: Timed out after 1000 usec (100000 CPU cycles) waiting for nmi_fired
  UVM_INFO @ 6069.499996 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.*.vmem could not be opened for r mode has 1 failures:
- Test chip_sw_kmac_app_rom has 1 failures.
  - 0.chip_sw_kmac_app_rom.32628021508437419931896408233048180541410246317267921426288988238131197706104
    Line 424, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_kmac_app_rom/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:563) [mem_bkdr_util[RamCtn0]] file kmac_app_rom_test_sim_dv.32.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(tl_h_i[*].a_source[(IDW - *)-:STIDW] == '0)' has 1 failures:
- Test chip_tl_errors has 1 failures.
  - 0.chip_tl_errors.57493209074068346887805346209218180586867679261429361480559672766647289550828
    Line 255, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_tl_errors/latest/run.log
```
      Offending '(tl_h_i[0].a_source[(IDW - 1)-:STIDW] == '0)'
  UVM_ERROR @ 3943.885976 us: (tlul_socket_m1.sv:101) [ASSERT FAILED] idInRange
  UVM_INFO @ 3943.885976 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (chip_jtag_base_vseq.sv:32) [chip_rv_dm_ndm_reset_vseq] wait timeout occurred! has 1 failures:
- Test chip_rv_dm_ndm_reset_req has 1 failures.
  - 0.chip_rv_dm_ndm_reset_req.88569973167892084880178597963260263889475205829708910608614973431625191258406
    Line 403, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_rv_dm_ndm_reset_req/latest/run.log
```
  UVM_FATAL @ 15720.178448 us: (chip_jtag_base_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_ndm_reset_vseq] wait timeout occurred!
  UVM_INFO @ 15720.178448 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Error-[CNST-CIF] Constraints inconsistency failure has 1 failures:
- Test chip_padctrl_attributes has 1 failures.
  - 0.chip_padctrl_attributes.18993471962594739135319961306792552426994811195300515897686518083859445090699
    Line 301, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_padctrl_attributes/latest/run.log
```
  Error-[CNST-CIF] Constraints inconsistency failure
  src/lowrisc_dv_dv_lib_0/dv_base_test.sv, 96
    Constraints are inconsistent and cannot be solved.
    Please check the inconsistent constraints being printed above and rewrite
    them.
```
UVM_FATAL @ * us: sequencer [sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item(). has 1 failures:
- Test chip_sw_dma_abort has 1 failures.
  - 0.chip_sw_dma_abort.51665099274583771878382554173985567073603062681572280739198972585569983550242
    Line 425, in log /nightly/runs/scratch/master/chip_darjeeling_asic-sim-vcs/0.chip_sw_dma_abort/latest/run.log
```
  UVM_FATAL @ 5751.869956 us: uvm_test_top.env.m_spi_device_agents0.sequencer [uvm_test_top.env.m_spi_device_agents0.sequencer] Item_done() called with no outstanding requests. Each call to item_done() must be paired with a previous call to get_next_item().
  UVM_INFO @ 5751.869956 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```