AES/MASKED Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	124.677us	1	1	100.00
V1	smoke	aes_smoke	5.000s	198.968us	1	1	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	216.342us	1	1	100.00
V1	csr_rw	aes_csr_rw	4.000s	99.210us	1	1	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	740.459us	1	1	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	126.077us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	166.375us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	99.210us	1	1	100.00
		aes_csr_aliasing	5.000s	126.077us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	algorithm	aes_smoke	5.000s	198.968us	1	1	100.00
		aes_config_error	6.000s	114.614us	1	1	100.00
		aes_stress	7.000s	560.313us	1	1	100.00
V2	key_length	aes_smoke	5.000s	198.968us	1	1	100.00
		aes_config_error	6.000s	114.614us	1	1	100.00
		aes_stress	7.000s	560.313us	1	1	100.00
V2	back2back	aes_stress	7.000s	560.313us	1	1	100.00
		aes_b2b	10.000s	435.522us	1	1	100.00
V2	backpressure	aes_stress	7.000s	560.313us	1	1	100.00
V2	multi_message	aes_smoke	5.000s	198.968us	1	1	100.00
		aes_config_error	6.000s	114.614us	1	1	100.00
		aes_stress	7.000s	560.313us	1	1	100.00
		aes_alert_reset	6.000s	504.176us	1	1	100.00
V2	failure_test	aes_man_cfg_err	4.000s	54.033us	1	1	100.00
		aes_config_error	6.000s	114.614us	1	1	100.00
		aes_alert_reset	6.000s	504.176us	1	1	100.00
V2	trigger_clear_test	aes_clear	35.000s	2.471ms	1	1	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	945.948us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	504.176us	1	1	100.00
V2	stress	aes_stress	7.000s	560.313us	1	1	100.00
V2	sideload	aes_stress	7.000s	560.313us	1	1	100.00
		aes_sideload	5.000s	129.879us	1	1	100.00
V2	deinitialization	aes_deinit	5.000s	131.204us	1	1	100.00
V2	stress_all	aes_stress_all	26.000s	596.591us	1	1	100.00
V2	alert_test	aes_alert_test	4.000s	63.507us	1	1	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	410.649us	1	1	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	410.649us	1	1	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	216.342us	1	1	100.00
		aes_csr_rw	4.000s	99.210us	1	1	100.00
		aes_csr_aliasing	5.000s	126.077us	1	1	100.00
		aes_same_csr_outstanding	4.000s	176.610us	1	1	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	216.342us	1	1	100.00
		aes_csr_rw	4.000s	99.210us	1	1	100.00
		aes_csr_aliasing	5.000s	126.077us	1	1	100.00
		aes_same_csr_outstanding	4.000s	176.610us	1	1	100.00
V2		TOTAL			13	13	100.00
V2S	reseeding	aes_reseed	5.000s	79.137us	1	1	100.00
V2S	fault_inject	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	358.751us	1	1	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.568ms	1	1	100.00
		aes_tl_intg_err	6.000s	378.819us	1	1	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	378.819us	1	1	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	504.176us	1	1	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	198.968us	1	1	100.00
		aes_stress	7.000s	560.313us	1	1	100.00
		aes_alert_reset	6.000s	504.176us	1	1	100.00
		aes_core_fi	24.000s	10.004ms	0	1	0.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	434.252us	1	1	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	61.299us	1	1	100.00
		aes_stress	7.000s	560.313us	1	1	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	560.313us	1	1	100.00
		aes_sideload	5.000s	129.879us	1	1	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	61.299us	1	1	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	61.299us	1	1	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	61.299us	1	1	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	61.299us	1	1	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	61.299us	1	1	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	560.313us	1	1	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	560.313us	1	1	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	143.673us	1	1	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	143.673us	1	1	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	5.000s	56.260us	1	1	100.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	143.673us	1	1	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	504.176us	1	1	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_ctr_fi	4.000s	98.485us	1	1	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	143.673us	1	1	100.00
		aes_control_fi	5.000s	48.434us	1	1	100.00
		aes_cipher_fi	5.000s	56.260us	1	1	100.00
V2S		TOTAL			10	11	90.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.000s	57.170us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			30	32	93.75

Failure Buckets

• UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:

  • Test aes_core_fi has 1 failures.

    • 0.aes_core_fi.108128911318292950236055590029704236718748772037632439204041349378429694352718
      Line 137, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_core_fi/latest/run.log

        UVM_FATAL @ 10004066765 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
        UVM_INFO @ 10004066765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:

  • Test aes_stress_all_with_rand_reset has 1 failures.

    • 0.aes_stress_all_with_rand_reset.11741207469323010588594195688079424533262215269213741891714584158094532734843
      Line 149, in log /nightly/runs/scratch/master/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

        UVM_FATAL @  57169945 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
        UVM_INFO @  57169945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---