DMA Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	dma_memory_smoke	dma_memory_smoke	7.000s	342.261us	1	1	100.00
V1	dma_handshake_smoke	dma_handshake_smoke	8.000s	1.439ms	1	1	100.00
V1	dma_generic_smoke	dma_generic_smoke	8.000s	1.589ms	1	1	100.00
V1	csr_hw_reset	dma_csr_hw_reset	4.000s	24.008us	1	1	100.00
V1	csr_rw	dma_csr_rw	4.000s	220.946us	1	1	100.00
V1	csr_bit_bash	dma_csr_bit_bash	9.000s	9.380ms	1	1	100.00
V1	csr_aliasing	dma_csr_aliasing	6.000s	362.028us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	dma_csr_mem_rw_with_rand_reset	4.000s	28.101us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	dma_csr_rw	4.000s	220.946us	1	1	100.00
		dma_csr_aliasing	6.000s	362.028us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	dma_memory_region_lock	dma_memory_region_lock	29.000s	2.025ms	1	1	100.00
V2	dma_handshake_stress	dma_handshake_stress	10.233m	239.918ms	1	1	100.00
V2	dma_memory_stress	dma_memory_stress	3.033m	122.886ms	1	1	100.00
V2	dma_generic_stress	dma_generic_stress	3.333m	77.186ms	1	1	100.00
V2	dma_handshake_mem_buffer_overflow	dma_handshake_stress	10.233m	239.918ms	1	1	100.00
V2	dma_abort	dma_abort	16.000s	2.362ms	1	1	100.00
V2	dma_stress_all	dma_stress_all	1.400m	25.807ms	1	1	100.00
V2	intr_test	dma_intr_test	3.000s	34.086us	1	1	100.00
V2	tl_d_oob_addr_access	dma_tl_errors	5.000s	411.860us	1	1	100.00
V2	tl_d_illegal_access	dma_tl_errors	5.000s	411.860us	1	1	100.00
V2	tl_d_outstanding_access	dma_csr_hw_reset	4.000s	24.008us	1	1	100.00
		dma_csr_rw	4.000s	220.946us	1	1	100.00
		dma_csr_aliasing	6.000s	362.028us	1	1	100.00
		dma_same_csr_outstanding	4.000s	263.437us	1	1	100.00
V2	tl_d_partial_access	dma_csr_hw_reset	4.000s	24.008us	1	1	100.00
		dma_csr_rw	4.000s	220.946us	1	1	100.00
		dma_csr_aliasing	6.000s	362.028us	1	1	100.00
		dma_same_csr_outstanding	4.000s	263.437us	1	1	100.00
V2		TOTAL			9	9	100.00
V2S	dma_illegal_addr_range	dma_mem_enabled	20.000s	708.175us	1	1	100.00
		dma_generic_stress	3.333m	77.186ms	1	1	100.00
		dma_handshake_stress	10.233m	239.918ms	1	1	100.00
V2S	tl_intg_err	dma_tl_intg_err	7.000s	92.672us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	dma_short_transfer	1.917m	31.124ms	1	1	100.00
		dma_longer_transfer	11.000s	860.512us	1	1	100.00
		TOTAL			21	21	100.00