EDN Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.740s	39.495us	1	1	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.630s	90.731us	1	1	100.00
V1	csr_rw	edn_csr_rw	1.730s	14.764us	1	1	100.00
V1	csr_bit_bash	edn_csr_bit_bash	4.710s	1.060ms	1	1	100.00
V1	csr_aliasing	edn_csr_aliasing	1.900s	38.712us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.020s	163.160us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.730s	14.764us	1	1	100.00
		edn_csr_aliasing	1.900s	38.712us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	firmware	edn_genbits	1.870s	68.041us	1	1	100.00
V2	csrng_commands	edn_genbits	1.870s	68.041us	1	1	100.00
V2	genbits	edn_genbits	1.870s	68.041us	1	1	100.00
V2	interrupts	edn_intr	1.750s	30.332us	1	1	100.00
V2	alerts	edn_alert	1.960s	194.018us	1	1	100.00
V2	errs	edn_err	1.900s	18.869us	1	1	100.00
V2	disable	edn_disable	1.770s	33.938us	1	1	100.00
		edn_disable_auto_req_mode	1.920s	36.355us	1	1	100.00
V2	stress_all	edn_stress_all	5.040s	585.600us	1	1	100.00
V2	intr_test	edn_intr_test	1.660s	22.873us	1	1	100.00
V2	alert_test	edn_alert_test	1.760s	17.343us	1	1	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	2.210s	131.878us	1	1	100.00
V2	tl_d_illegal_access	edn_tl_errors	2.210s	131.878us	1	1	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.630s	90.731us	1	1	100.00
		edn_csr_rw	1.730s	14.764us	1	1	100.00
		edn_csr_aliasing	1.900s	38.712us	1	1	100.00
		edn_same_csr_outstanding	1.850s	54.899us	1	1	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.630s	90.731us	1	1	100.00
		edn_csr_rw	1.730s	14.764us	1	1	100.00
		edn_csr_aliasing	1.900s	38.712us	1	1	100.00
		edn_same_csr_outstanding	1.850s	54.899us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	tl_intg_err	edn_sec_cm	7.570s	558.586us	1	1	100.00
		edn_tl_intg_err	2.920s	149.101us	1	1	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.690s	228.411us	1	1	100.00
V2S	sec_cm_config_mubi	edn_alert	1.960s	194.018us	1	1	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	7.570s	558.586us	1	1	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	7.570s	558.586us	1	1	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	7.570s	558.586us	1	1	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	7.570s	558.586us	1	1	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.960s	194.018us	1	1	100.00
		edn_sec_cm	7.570s	558.586us	1	1	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.960s	194.018us	1	1	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	2.920s	149.101us	1	1	100.00
V2S		TOTAL			3	3	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	24.400s	11.378ms	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			21	21	100.00