HMAC Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke hmac_smoke 10.180s 1.240ms 1 1 100.00
V1 csr_hw_reset hmac_csr_hw_reset 1.840s 89.690us 1 1 100.00
V1 csr_rw hmac_csr_rw 1.630s 55.086us 1 1 100.00
V1 csr_bit_bash hmac_csr_bit_bash 4.870s 728.696us 1 1 100.00
V1 csr_aliasing hmac_csr_aliasing 3.040s 56.482us 1 1 100.00
V1 csr_mem_rw_with_rand_reset hmac_csr_mem_rw_with_rand_reset 1.790s 23.644us 1 1 100.00
V1 regwen_csr_and_corresponding_lockable_csr hmac_csr_rw 1.630s 55.086us 1 1 100.00
hmac_csr_aliasing 3.040s 56.482us 1 1 100.00
V1 TOTAL 6 6 100.00
V2 long_msg hmac_long_msg 4.260s 481.613us 1 1 100.00
V2 back_pressure hmac_back_pressure 57.010s 5.897ms 1 1 100.00
V2 test_vectors hmac_test_sha256_vectors 9.150s 351.878us 1 1 100.00
hmac_test_sha384_vectors 19.380s 231.044us 1 1 100.00
hmac_test_sha512_vectors 6.502m 47.443ms 1 1 100.00
hmac_test_hmac256_vectors 9.980s 320.793us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 2.492ms 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1.845ms 1 1 100.00
V2 burst_wr hmac_burst_wr 13.190s 2.796ms 1 1 100.00
V2 datapath_stress hmac_datapath_stress 6.050s 220.596us 1 1 100.00
V2 error hmac_error 53.170s 26.720ms 1 1 100.00
V2 wipe_secret hmac_wipe_secret 1.026m 5.127ms 1 1 100.00
V2 save_and_restore hmac_smoke 10.180s 1.240ms 1 1 100.00
hmac_long_msg 4.260s 481.613us 1 1 100.00
hmac_back_pressure 57.010s 5.897ms 1 1 100.00
hmac_datapath_stress 6.050s 220.596us 1 1 100.00
hmac_burst_wr 13.190s 2.796ms 1 1 100.00
hmac_stress_all 8.590s 1.140ms 1 1 100.00
V2 fifo_empty_status_interrupt hmac_smoke 10.180s 1.240ms 1 1 100.00
hmac_long_msg 4.260s 481.613us 1 1 100.00
hmac_back_pressure 57.010s 5.897ms 1 1 100.00
hmac_datapath_stress 6.050s 220.596us 1 1 100.00
hmac_wipe_secret 1.026m 5.127ms 1 1 100.00
hmac_test_sha256_vectors 9.150s 351.878us 1 1 100.00
hmac_test_sha384_vectors 19.380s 231.044us 1 1 100.00
hmac_test_sha512_vectors 6.502m 47.443ms 1 1 100.00
hmac_test_hmac256_vectors 9.980s 320.793us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 2.492ms 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1.845ms 1 1 100.00
V2 wide_digest_configurable_key_length hmac_smoke 10.180s 1.240ms 1 1 100.00
hmac_long_msg 4.260s 481.613us 1 1 100.00
hmac_back_pressure 57.010s 5.897ms 1 1 100.00
hmac_datapath_stress 6.050s 220.596us 1 1 100.00
hmac_burst_wr 13.190s 2.796ms 1 1 100.00
hmac_error 53.170s 26.720ms 1 1 100.00
hmac_wipe_secret 1.026m 5.127ms 1 1 100.00
hmac_test_sha256_vectors 9.150s 351.878us 1 1 100.00
hmac_test_sha384_vectors 19.380s 231.044us 1 1 100.00
hmac_test_sha512_vectors 6.502m 47.443ms 1 1 100.00
hmac_test_hmac256_vectors 9.980s 320.793us 1 1 100.00
hmac_test_hmac384_vectors 9.220s 2.492ms 1 1 100.00
hmac_test_hmac512_vectors 10.050s 1.845ms 1 1 100.00
hmac_stress_all 8.590s 1.140ms 1 1 100.00
V2 stress_all hmac_stress_all 8.590s 1.140ms 1 1 100.00
V2 alert_test hmac_alert_test 1.650s 23.345us 1 1 100.00
V2 intr_test hmac_intr_test 1.590s 57.210us 1 1 100.00
V2 tl_d_oob_addr_access hmac_tl_errors 2.870s 129.367us 1 1 100.00
V2 tl_d_illegal_access hmac_tl_errors 2.870s 129.367us 1 1 100.00
V2 tl_d_outstanding_access hmac_csr_hw_reset 1.840s 89.690us 1 1 100.00
hmac_csr_rw 1.630s 55.086us 1 1 100.00
hmac_csr_aliasing 3.040s 56.482us 1 1 100.00
hmac_same_csr_outstanding 2.570s 199.602us 1 1 100.00
V2 tl_d_partial_access hmac_csr_hw_reset 1.840s 89.690us 1 1 100.00
hmac_csr_rw 1.630s 55.086us 1 1 100.00
hmac_csr_aliasing 3.040s 56.482us 1 1 100.00
hmac_same_csr_outstanding 2.570s 199.602us 1 1 100.00
V2 TOTAL 17 17 100.00
V2S tl_intg_err hmac_sec_cm 2.070s 352.807us 1 1 100.00
hmac_tl_intg_err 3.290s 736.195us 1 1 100.00
V2S sec_cm_bus_integrity hmac_tl_intg_err 3.290s 736.195us 1 1 100.00
V2S TOTAL 2 2 100.00
V3 write_config_and_secret_key_during_msg_wr hmac_smoke 10.180s 1.240ms 1 1 100.00
V3 stress_reset hmac_stress_reset 3.970s 722.192us 1 1 100.00
V3 stress_all_with_rand_reset hmac_stress_all_with_rand_reset 1.130m 11.726ms 1 1 100.00
V3 TOTAL 2 2 100.00
Unmapped tests hmac_directed 4.820s 701.167us 1 1 100.00
TOTAL 28 28 100.00