I2C Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: `209351c`

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	host_smoke	i2c_host_smoke	22.470s	3.964ms	1	1	100.00
V1	target_smoke	i2c_target_smoke	13.310s	4.661ms	1	1	100.00
V1	csr_hw_reset	i2c_csr_hw_reset	1.750s	56.605us	1	1	100.00
V1	csr_rw	i2c_csr_rw	1.570s	36.822us	1	1	100.00
V1	csr_bit_bash	i2c_csr_bit_bash	3.090s	268.871us	1	1	100.00
V1	csr_aliasing	i2c_csr_aliasing	2.750s	75.654us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	i2c_csr_mem_rw_with_rand_reset	1.800s	53.957us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	i2c_csr_rw	1.570s	36.822us	1	1	100.00
		i2c_csr_aliasing	2.750s	75.654us	1	1	100.00
V1		TOTAL			7	7	100.00
V2	host_error_intr	i2c_host_error_intr	3.710s	516.888us	1	1	100.00
V2	host_stress_all	i2c_host_stress_all	17.799m	27.642ms	0	1	0.00
V2	host_maxperf	i2c_host_perf	21.400s	6.606ms	1	1	100.00
V2	host_override	i2c_host_override	1.480s	59.654us	1	1	100.00
V2	host_fifo_watermark	i2c_host_fifo_watermark	2.258m	3.923ms	1	1	100.00
V2	host_fifo_overflow	i2c_host_fifo_overflow	1.250m	11.971ms	1	1	100.00
V2	host_fifo_reset	i2c_host_fifo_reset_fmt	1.950s	419.360us	1	1	100.00
		i2c_host_fifo_fmt_empty	6.960s	347.545us	1	1	100.00
		i2c_host_fifo_reset_rx	6.670s	701.110us	1	1	100.00
V2	host_fifo_full	i2c_host_fifo_full	1.019m	5.819ms	1	1	100.00
V2	host_timeout	i2c_host_stretch_timeout	21.380s	604.238us	1	1	100.00
V2	i2c_host_mode_toggle	i2c_host_mode_toggle	2.740s	274.505us	0	1	0.00
V2	target_glitch	i2c_target_glitch	8.060s	2.535ms	1	1	100.00
V2	target_stress_all	i2c_target_stress_all	5.025m	39.842ms	1	1	100.00
V2	target_maxperf	i2c_target_perf	4.600s	917.671us	1	1	100.00
V2	target_fifo_empty	i2c_target_stress_rd	13.890s	1.702ms	1	1	100.00
		i2c_target_intr_smoke	4.540s	8.788ms	1	1	100.00
V2	target_fifo_reset	i2c_target_fifo_reset_acq	2.090s	387.260us	1	1	100.00
		i2c_target_fifo_reset_tx	2.530s	414.219us	1	1	100.00
V2	target_fifo_full	i2c_target_stress_wr	10.350s	20.438ms	1	1	100.00
		i2c_target_stress_rd	13.890s	1.702ms	1	1	100.00
		i2c_target_intr_stress_wr	3.770m	40.052ms	1	1	100.00
V2	target_timeout	i2c_target_timeout	5.060s	5.452ms	1	1	100.00
V2	target_clock_stretch	i2c_target_stretch	10.370s	1.497ms	1	1	100.00
V2	bad_address	i2c_target_bad_addr	3.850s	4.651ms	1	1	100.00
V2	target_mode_glitch	i2c_target_hrst	15.140s	10.218ms	0	1	0.00
V2	target_fifo_watermark	i2c_target_fifo_watermarks_acq	3.040s	538.045us	1	1	100.00
		i2c_target_fifo_watermarks_tx	2.360s	339.168us	1	1	100.00
V2	host_mode_config_perf	i2c_host_perf	21.400s	6.606ms	1	1	100.00
		i2c_host_perf_precise	8.680s	2.541ms	1	1	100.00
V2	host_mode_clock_stretching	i2c_host_stretch_timeout	21.380s	604.238us	1	1	100.00
V2	target_mode_tx_stretch_ctrl	i2c_target_tx_stretch_ctrl	2.940s	151.693us	1	1	100.00
V2	target_mode_nack_generation	i2c_target_nack_acqfull	3.170s	10.325ms	1	1	100.00
		i2c_target_nack_acqfull_addr	2.650s	509.458us	1	1	100.00
		i2c_target_nack_txstretch	2.050s	2.338ms	1	1	100.00
V2	host_mode_halt_on_nak	i2c_host_may_nack	4.660s	7.070ms	1	1	100.00
V2	target_mode_smbus_maxlen	i2c_target_smbus_maxlen	3.800s	495.911us	1	1	100.00
V2	alert_test	i2c_alert_test	1.530s	17.422us	1	1	100.00
V2	intr_test	i2c_intr_test	2.060s	68.785us	1	1	100.00
V2	tl_d_oob_addr_access	i2c_tl_errors	2.150s	49.248us	1	1	100.00
V2	tl_d_illegal_access	i2c_tl_errors	2.150s	49.248us	1	1	100.00
V2	tl_d_outstanding_access	i2c_csr_hw_reset	1.750s	56.605us	1	1	100.00
		i2c_csr_rw	1.570s	36.822us	1	1	100.00
		i2c_csr_aliasing	2.750s	75.654us	1	1	100.00
		i2c_same_csr_outstanding	2.370s	26.565us	1	1	100.00
V2	tl_d_partial_access	i2c_csr_hw_reset	1.750s	56.605us	1	1	100.00
		i2c_csr_rw	1.570s	36.822us	1	1	100.00
		i2c_csr_aliasing	2.750s	75.654us	1	1	100.00
		i2c_same_csr_outstanding	2.370s	26.565us	1	1	100.00
V2		TOTAL			35	38	92.11
V2S	tl_intg_err	i2c_tl_intg_err	2.520s	304.649us	1	1	100.00
		i2c_sec_cm	1.600s	149.202us	1	1	100.00
V2S	sec_cm_bus_integrity	i2c_tl_intg_err	2.520s	304.649us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	host_stress_all_with_rand_reset	i2c_host_stress_all_with_rand_reset	10.790s	3.122ms	0	1	0.00
V3	target_error_intr	i2c_target_unexp_stop	2.010s	108.359us	0	1	0.00
V3	target_stress_all_with_rand_reset	i2c_target_stress_all_with_rand_reset	28.820s	990.990us	0	1	0.00
V3		TOTAL			0	3	0.00
		TOTAL			44	50	88.00

Failure Buckets

UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared: has 2 failures:

Test i2c_host_stress_all has 1 failures.

0.i2c_host_stress_all.101480506669898446909287851448882590268856936379555258108614591372859578071437
Line 144, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all/latest/run.log

  UVM_ERROR @ 27642412976 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @8748554

Test i2c_host_mode_toggle has 1 failures.

0.i2c_host_mode_toggle.58377156540656993905212327758964373193535125955384944662125680254985916352259
Line 80, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_mode_toggle/latest/run.log

  UVM_ERROR @ 274505194 ps: (i2c_scoreboard.sv:716) [uvm_test_top.env.scoreboard] controller_mode_rd_obs_fifo item uncompared:
  ----------------------------------------------------
  Name            Type                Size  Value
  ----------------------------------------------------
  mon_dut_item    i2c_item            -     @35403

UVM_ERROR (cip_base_vseq.sv:928) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test i2c_host_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_host_stress_all_with_rand_reset.60860144024576441214511453037754133808392648252292219600004901565220275225813
    Line 86, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_host_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3122249445 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 3122249445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test i2c_target_stress_all_with_rand_reset has 1 failures.
  - 0.i2c_target_stress_all_with_rand_reset.72962844237546166937521107290597709417849673431239463093048400429108473643612
    Line 102, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 990989698 ps: (cip_base_vseq.sv:928) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 990989698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [*] vs * [*]) has 1 failures:
- Test i2c_target_unexp_stop has 1 failures.
  - 0.i2c_target_unexp_stop.105801539707194486681751618291601509439844409158539738744179885548062113268131
    Line 73, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_unexp_stop/latest/run.log
```
  UVM_ERROR @ 108358637 ps: (i2c_scoreboard.sv:682) [uvm_test_top.env.scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (255 [0xff] vs 226 [0xe2])
  UVM_INFO @ 108358637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred! has 1 failures:
- Test i2c_target_hrst has 1 failures.
  - 0.i2c_target_hrst.13082614520233802145024489848071772503318840846447352136079608329827905545320
    Line 74, in log /nightly/runs/scratch/master/i2c-sim-vcs/0.i2c_target_hrst/latest/run.log
```
  UVM_FATAL @ 10218097222 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
  UVM_INFO @ 10218097222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```