| V1 |
smoke |
keymgr_dpe_smoke |
13.170s |
3.093ms |
1 |
1 |
100.00 |
| V1 |
csr_hw_reset |
keymgr_dpe_csr_hw_reset |
1.820s |
187.283us |
1 |
1 |
100.00 |
| V1 |
csr_rw |
keymgr_dpe_csr_rw |
1.660s |
14.199us |
1 |
1 |
100.00 |
| V1 |
csr_bit_bash |
keymgr_dpe_csr_bit_bash |
13.850s |
2.452ms |
1 |
1 |
100.00 |
| V1 |
csr_aliasing |
keymgr_dpe_csr_aliasing |
4.220s |
447.321us |
1 |
1 |
100.00 |
| V1 |
csr_mem_rw_with_rand_reset |
keymgr_dpe_csr_mem_rw_with_rand_reset |
1.940s |
80.853us |
1 |
1 |
100.00 |
| V1 |
regwen_csr_and_corresponding_lockable_csr |
keymgr_dpe_csr_rw |
1.660s |
14.199us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.220s |
447.321us |
1 |
1 |
100.00 |
| V1 |
|
TOTAL |
|
|
6 |
6 |
100.00 |
| V2 |
intr_test |
keymgr_dpe_intr_test |
1.680s |
23.785us |
1 |
1 |
100.00 |
| V2 |
alert_test |
keymgr_dpe_alert_test |
1.680s |
14.030us |
1 |
1 |
100.00 |
| V2 |
tl_d_oob_addr_access |
keymgr_dpe_tl_errors |
2.330s |
119.212us |
1 |
1 |
100.00 |
| V2 |
tl_d_illegal_access |
keymgr_dpe_tl_errors |
2.330s |
119.212us |
1 |
1 |
100.00 |
| V2 |
tl_d_outstanding_access |
keymgr_dpe_csr_hw_reset |
1.820s |
187.283us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.660s |
14.199us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.220s |
447.321us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.450s |
121.366us |
1 |
1 |
100.00 |
| V2 |
tl_d_partial_access |
keymgr_dpe_csr_hw_reset |
1.820s |
187.283us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_rw |
1.660s |
14.199us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_csr_aliasing |
4.220s |
447.321us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_same_csr_outstanding |
2.450s |
121.366us |
1 |
1 |
100.00 |
| V2 |
|
TOTAL |
|
|
4 |
4 |
100.00 |
| V2S |
tl_intg_err |
keymgr_dpe_sec_cm |
8.000s |
710.987us |
1 |
1 |
100.00 |
|
|
keymgr_dpe_tl_intg_err |
3.800s |
377.606us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error |
keymgr_dpe_shadow_reg_errors |
2.940s |
204.321us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_read_clear_staged_value |
keymgr_dpe_shadow_reg_errors |
2.940s |
204.321us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_storage_error |
keymgr_dpe_shadow_reg_errors |
2.940s |
204.321us |
1 |
1 |
100.00 |
| V2S |
shadowed_reset_glitch |
keymgr_dpe_shadow_reg_errors |
2.940s |
204.321us |
1 |
1 |
100.00 |
| V2S |
shadow_reg_update_error_with_csr_rw |
keymgr_dpe_shadow_reg_errors_with_csr_rw |
5.160s |
1.012ms |
1 |
1 |
100.00 |
| V2S |
prim_count_check |
keymgr_dpe_sec_cm |
8.000s |
710.987us |
1 |
1 |
100.00 |
| V2S |
prim_fsm_check |
keymgr_dpe_sec_cm |
8.000s |
710.987us |
1 |
1 |
100.00 |
| V2S |
|
TOTAL |
|
|
4 |
4 |
100.00 |
|
|
TOTAL |
|
|
14 |
14 |
100.00 |