KMAC/MASKED Simulation Results

Wednesday June 11 2025 17:04:17 UTC

GitHub Revision: 209351c

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	5.210s	220.994us	1	1	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.800s	79.211us	1	1	100.00
V1	csr_rw	kmac_csr_rw	1.840s	89.041us	1	1	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	8.660s	1.477ms	1	1	100.00
V1	csr_aliasing	kmac_csr_aliasing	3.820s	149.502us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	3.480s	84.439us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.840s	89.041us	1	1	100.00
		kmac_csr_aliasing	3.820s	149.502us	1	1	100.00
V1	mem_walk	kmac_mem_walk	1.900s	20.193us	1	1	100.00
V1	mem_partial_access	kmac_mem_partial_access	2.100s	66.218us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	2.684m	4.377ms	1	1	100.00
V2	burst_write	kmac_burst_write	20.716m	31.555ms	1	1	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	32.500m	177.355ms	1	1	100.00
		kmac_test_vectors_sha3_256	27.380s	5.008ms	1	1	100.00
		kmac_test_vectors_sha3_384	26.220s	1.797ms	1	1	100.00
		kmac_test_vectors_sha3_512	15.800s	5.623ms	1	1	100.00
		kmac_test_vectors_shake_128	3.222m	46.866ms	1	1	100.00
		kmac_test_vectors_shake_256	24.201m	34.724ms	1	1	100.00
		kmac_test_vectors_kmac	3.240s	40.423us	1	1	100.00
		kmac_test_vectors_kmac_xof	3.030s	47.624us	1	1	100.00
V2	sideload	kmac_sideload	2.046m	11.352ms	1	1	100.00
V2	app	kmac_app	3.140m	16.761ms	1	1	100.00
V2	app_with_partial_data	kmac_app_with_partial_data	2.775m	4.233ms	1	1	100.00
V2	entropy_refresh	kmac_entropy_refresh	1.333m	18.767ms	1	1	100.00
V2	error	kmac_error	1.676m	10.182ms	1	1	100.00
V2	key_error	kmac_key_error	3.920s	1.517ms	1	1	100.00
V2	sideload_invalid	kmac_sideload_invalid	4.580s	188.390us	1	1	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	12.500s	1.020ms	1	1	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	2.010s	96.192us	1	1	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	19.180s	3.800ms	1	1	100.00
V2	lc_escalation	kmac_lc_escalation	2.330s	47.844us	1	1	100.00
V2	stress_all	kmac_stress_all	25.444m	39.688ms	1	1	100.00
V2	intr_test	kmac_intr_test	1.840s	47.045us	1	1	100.00
V2	alert_test	kmac_alert_test	1.710s	61.276us	1	1	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.270s	481.877us	1	1	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.270s	481.877us	1	1	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.800s	79.211us	1	1	100.00
		kmac_csr_rw	1.840s	89.041us	1	1	100.00
		kmac_csr_aliasing	3.820s	149.502us	1	1	100.00
		kmac_same_csr_outstanding	2.330s	53.056us	1	1	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.800s	79.211us	1	1	100.00
		kmac_csr_rw	1.840s	89.041us	1	1	100.00
		kmac_csr_aliasing	3.820s	149.502us	1	1	100.00
		kmac_same_csr_outstanding	2.330s	53.056us	1	1	100.00
V2		TOTAL			26	26	100.00
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.450s	150.594us	1	1	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.450s	150.594us	1	1	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.450s	150.594us	1	1	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.450s	150.594us	1	1	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	3.930s	321.605us	1	1	100.00
V2S	tl_intg_err	kmac_sec_cm	27.270s	4.633ms	1	1	100.00
		kmac_tl_intg_err	1.750s	13.669us	0	1	0.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	1.750s	13.669us	0	1	0.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	2.330s	47.844us	1	1	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	5.210s	220.994us	1	1	100.00
V2S	sec_cm_key_sideload	kmac_sideload	2.046m	11.352ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.450s	150.594us	1	1	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	27.270s	4.633ms	1	1	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	27.270s	4.633ms	1	1	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	27.270s	4.633ms	1	1	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	5.210s	220.994us	1	1	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	2.330s	47.844us	1	1	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	27.270s	4.633ms	1	1	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	2.449m	31.719ms	1	1	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	5.210s	220.994us	1	1	100.00
V2S		TOTAL			4	5	80.00
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	47.570s	5.718ms	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			38	40	95.00

Failure Buckets

• UVM_ERROR (kmac_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 1 failures:

  • Test kmac_stress_all_with_rand_reset has 1 failures.

    • 0.kmac_stress_all_with_rand_reset.72679893500739681193398841718281792184307749725338271434548100339427130773074
      Line 130, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 5718068969 ps: (kmac_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
        UVM_INFO @ 5718068969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Offending '(d2h.d_error || ((d2h.d_data & *) == (exp_vals[*] & *)))' has 1 failures:

  • Test kmac_tl_intg_err has 1 failures.

    • 0.kmac_tl_intg_err.73445495921236576293816048363676757983725461730267249999453930507128210634744
      Line 75, in log /nightly/runs/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest/run.log

            Offending '(d2h.d_error || ((d2h.d_data & 'hffffffff) == (exp_vals[42] & 'hffffffff)))'
        UVM_ERROR @  13668957 ps: (kmac_csr_assert_fpv.sv:518) [ASSERT FAILED] prefix_3_rd_A
        UVM_INFO @  13668957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---